Abstract: The present invention provides a method for recovering nickel hydroxide and nickel sulfate from nickel-containing materials, wherein the nickel-containing materials are crushed and pulverized and then leached with sulfuric acid, leached residue separation and filtrate separation are performed and then the pH is adjusted to recover nickel hydroxide, and the recovered nickel hydroxide is further subjected to a sulfation reaction to recover nickel sulfate.

Abstract: The present invention provides a method for recovering high-efficiency lithium from a low-concentration lithium waste liquid, and lithium carbonate produced thereby, the method comprising the steps of: adsorbing lithium-containing metal ions from a lithium waste liquid onto an electrode in an electric adsorption system, and desorbing the metal ions adsorbed on the electrode with a desorption solution (S10); preparing an insoluble lithium compound by adding an aluminum source to the desorption solution (S20); preparing a leachate by acid leaching or roasting/water leaching of the insoluble lithium compound (S30); and producing at least one of lithium phosphate, liquid sulfate, and lithium carbonate from the leachate.

Abstract: The present invention provides a method for recovering lithium from a waste primary lithium battery leachate and producing lithium chloride therefrom, wherein a lithium component is separated as a precipitated and insoluble lithium compound, which is then converted into a lithium chloride solution through wet conversion, followed by crystallization, thereby preparing a lithium chloride powder.

Abstract: The present disclosure relates to a method for recovery of valuable metals and a zeolite-containing material from a waste cathode material reaction vessel, in which valuable metals and a zeolite-containing material are recovered from a waste cathode material reaction vessel being discarded, and recycled as resources, thus reducing waste from the waste cathode material reaction vessel.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.

Abstract: A method for driving a nonvolatile memory device using a resistive element is provided. The method includes storing data in a page buffer, the data including a first data block and a second data block, writing the first data block to a memory cell, performing a verify-read operation on the first data block of the memory cell region, writing the second data block to the memory cell region, and performing a verify-read operation on the second data block of the memory cell region, wherein the first data block and the second data block are smaller than the page buffer in size.

Abstract: A method for driving a nonvolatile memory device using a resistive element is provided. The method includes storing data in a page buffer, the data including a first data block and a second data block, writing the first data block to a memory cell, performing a verify-read operation on the first data block of the memory cell region, writing the second data block to the memory cell region, and performing a verify-read operation on the second data block of the memory cell region, wherein the first data block and the second data block are smaller than the page buffer in size.

Abstract: A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

Abstract: A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

Abstract: A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

Abstract: A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

Abstract: Provided an apparatus and method for controlling luminance of a display device. The apparatus includes an analog digital converter (ADC), a video processor, a control unit, and a display unit. The ADC converts input image data into a digital signal. The video processor converts the digital signal output from the ADC into a format suitable for a display module. The control unit receives the formatted signal from the video processor and converts a luminance level of the formatted signal into modified luminance levels so as to reduce differences between output luminance levels across pixel regions of the display module. The display unit displays the input image data using the formatted signal according to the modified luminance levels.

Abstract: We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing data to memory cells includes an input and output line for transferring data to be written to each of the memory cells. A precharge control circuit is adapted to generate a precharge control signal for controlling a precharge disable state of the input and output line after application of a first write command. The disable state of the precharge control signal is maintained even after application of a second write command when performing a continuous write operation responsive to the second write command application without other commands applied subsequent to the first write command application. Avoiding precharging the input and output line in a continuous write operation, reduces current consumption.

Abstract: An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit includes an internal driving unit, an internal transmission unit, and an internal sensing unit. The internal driving unit is configured to generate a driving current and a preliminary voltage responsive to an external supply voltage that is supplied from external to the semiconductor memory device, and it varies a magnitude of the driving current responsive to a driving control signal. The internal transmission unit is configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and to vary a level of the internal supply voltage to be at least a defined voltage difference less than a boosted voltage. The boosted voltage is greater than the external supply voltage.

Abstract: We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing data to memory cells includes an input and output line for transferring data to be written to each of the memory cells. A precharge control circuit is adapted to generate a precharge control signal for controlling a precharge disable state of the input and output line after application of a first write command. The disable state of the precharge control signal is maintained even after application of a second write command when performing a continuous write operation responsive to the second write command application without other commands applied subsequent to the first write command application. Avoiding precharging the input and output line in a continuous write operation, reduces current consumption.

Abstract: An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit includes an internal driving unit, an internal transmission unit, and an internal sensing unit. The internal driving unit is configured to generate a driving current and a preliminary voltage responsive to an external supply voltage that is supplied from external to the semiconductor memory device, and it varies a magnitude of the driving current responsive to a driving control signal. The internal transmission unit is configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and to vary a level of the internal supply voltage to be at least a defined voltage difference less than a boosted voltage. The boosted voltage is greater than the external supply voltage.