Abstract: The wide-angle emission filter includes a base matrix, a photoresist, and a colorant. The base matrix has a flat shape and including a transparent material. The base matrix does not generate fluorescent light or phosphorescent light by an excitation light. The photoresist is disposed in the base matrix. The photoresist is fixed in a solid state through at least one method selected from the group consisting of thermal hardening, photo hardening, and drying. The colorant is disposed in the base matrix and includes light having a predetermined wavelength range. The wide-angle emission filter filters the excitation light regardless of an incident angle of the excitation light.

Abstract: The wide-angle emission filter includes a base matrix, a photoresist, and a colorant. The base matrix has a flat shape and including a transparent material. The base matrix does not generate fluorescent light or phosphorescent light by an excitation light. The photoresist is disposed in the base matrix. The photoresist is fixed in a solid state through at least one method selected from the group consisting of thermal hardening, photo hardening, and drying. The colorant is disposed in the base matrix and includes light having a predetermined wavelength range. The wide-angle emission filter filters the excitation light regardless of an incident angle of the excitation light.

Abstract: The present invention relates to an image sensor sensor having improved spectral characteristics, and improves a color characteristic and sensitivity of an image sensor by implementing an image sensor sensor using a stacked substrate structure having photodiodes formed on each of two substrates, and generating a color signal having improved spectral characteristics based on an electrical signal outputted from each of the photodiodes formed on two substrates.

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract: The present invention relates to a CMOS image sensor including an infrared pixel with enhanced spectral characteristics in which a stepped portion is formed between color filters of RGB pixels and a filter of an infrared pixel, and a manufacturing method thereof. A stepped portion is formed between color filters and an infrared filter according to respective pixels and the thicknesses of the filters are arbitrarily adjusted regardless of the characteristics of material in the formation of the color filters and the infrared filter, so that crosstalk characteristics are improved.

Abstract: The present invention provides relates to a substrate separation-type three-dimensional chip stacking image sensor of which a noise characteristic is improved by separately implementing an image sensor circuit as a first semiconductor chip and a second semiconductor chip and physically separating substrate respectively forming the first semiconductor chip and the second semiconductor chip, and a method for manufacturing the same. The present invention has the advantage that even though a plurality of circuit blocks are formed on one semiconductor substrate, the substrate is physically separated such that the separated substrates independently operate.

Abstract: The present invention relates to a CMOS image sensor including a color microlens, in which the color characteristics of a microlens are improved by replacing a microlens made of a transparent material with a material having characteristics similar to those of a color filter, and a manufacturing method thereof. In accordance with the CMOS image sensor including a color microlens and the manufacturing method thereof according to the present invention, color characteristics is improved. Since formation processes of a color filter and a microlens are performed at one time, additional processes for planarization and step difference adjustment are not necessary, so that an entire process is simplified. In the progress of light, since there is no interface between materials, reflection, refraction and the like are reduced, so that it is possible to increase light efficiency.

Abstract: The present invention relates to a CMOS image sensor including an infrared pixel with enhanced spectral characteristics in which a stepped portion is formed between color filters of RGB pixels and a filter of an infrared pixel, and a manufacturing method thereof. A stepped portion is formed between color filters and an infrared filter according to respective pixels and the thicknesses of the filters are arbitrarily adjusted regardless of the characteristics of material in the formation of the color filters and the infrared filter, so that crosstalk characteristics are improved.

Abstract: The present invention relates to a chip-stacked image sensor and to a method for manufacturing the same. More particularly, the present invention relates to a chip-stacked image sensor having a heterogeneous junction structure and to a method for manufacturing the same, in which a first semiconductor chip and a second semiconductor chip are manufactured using substrate materials suitable for the characteristics of sensors formed on each semiconductor substrate, and the semiconductor chips are stacked to form an image sensor. According to the chip-stacked image sensor having a heterogeneous junction structure and the method for manufacturing the same, the material for a first semiconductor substrate used in a first semiconductor chip and the material for a second semiconductor substrate used in a second semiconductor chip are different from each other, thus enabling characteristics of sensors formed on each semiconductor chip to be properly exhibited.

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure includes: (a) a first process of bonding a device wafer and a handling wafer; (b) a second process of thinning a back side of an Si substrate which is formed on the device wafer, after the first process; (c) a third process of forming an anti-reflective layer and a PMD (preferential metal deposition) dielectric layer, after the second process; (d) a fourth process of forming vias on back sides of super contacts which are formed on the Si substrate, after the third process; and (e) a fifth process of forming a pad, after the fourth process.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.