Patents by Inventor Jun Ho Yoon

Jun Ho Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966919
    Abstract: Various example embodiments of the disclosure relate to an electronic device and a wireless communication connection control method thereof.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Ho Kang, Jinhyun Park, Ye-Ji Yoon, Jun-Hak Lim, Wontae Chae, Jongmu Choi, Bokun Choi, Doo-Suk Kang, Sun-Kee Lee, Moonsoo Kim, Eun Jung Hyun
  • Publication number: 20240084444
    Abstract: According to an embodiment of the present invention, there is provided method for preparing low-loss hydrogenated amorphous silicon nitride that is transparent in visible light comprising: a step in which a substrate is provided; a step in which a Plasma Enhanced Chemical Vapor Deposition (PECVD) which is used to insert H2 gas and SiH4 gas into a chamber is used to deposit a dielectric layer 200 onto the substrate, and gases inserted into the chamber further comprise N2 gas apart from the H2 gas and the SiH4 gas. Further, there is provided a method for preparing low-loss hydrogenated amorphous silicon oxide that is transparent in visible light further comprising O2 gas apart from the H2 gas and the SiH4 gas. Further, there is provided a method for preparing low-loss hydrogenated amorphous silicon that is transparent in visible light further comprising Ar gas apart from the H2 gas and the SiH4 gas.
    Type: Application
    Filed: January 13, 2022
    Publication date: March 14, 2024
    Inventors: Jun Suk RHO, Young Hwan YANG, Gwan Ho YOON
  • Publication number: 20230378394
    Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 23, 2023
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventors: Dae Hong MIN, Jun Ho YOON, Woo Cheol GWAK, Jin Woo HUH, Yong Hyun BAEK
  • Patent number: 11710706
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: July 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Publication number: 20230207933
    Abstract: The present invention is provided with a secondary battery comprising: an electrode assembly to which an electrode lead is bonded; a pouch configured to accommodate the electrode assembly and provided with a sealing part; and a lead film configured to seal a portion between the sealing part and the electrode lead, wherein a pattern means configured to pattern the sealing part and the lead film so as to increase in bonding area between the sealing part and the lead film is provided on a bonding portion between the sealing part and the lead film. Therefore, bonding force and sealing force between the lead film and the sealing part may increase.
    Type: Application
    Filed: January 27, 2022
    Publication date: June 29, 2023
    Applicant: LG Energy Solution, Ltd.
    Inventors: Yoon Beom Lee, Jun Ho Yoon, Chang Min Han
  • Publication number: 20230204529
    Abstract: Provided is a method for analyzing the content of D-lactic repeating units (D content) in polylactic acid that has a feature that the D content in polylactic acid can be quickly and accurately analyzed by using NMR data of polylactic acid and hypothetical polylactic acid without special chemical treatment for polylactic acid.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 29, 2023
    Inventors: Hyunchul JUNG, Jun Ho YOON, Wan Kyu OH, Yujin AN
  • Publication number: 20230170118
    Abstract: A coil component includes: a body having first and second surfaces opposing each other; and a coil portion embedded within the body, wherein the coil portion includes first and second coil patterns, a first lead-out portion and a first dummy lead-out portion respectively extending from the first coil pattern, and respectively exposed to the first and second surfaces of the body, while being spaced apart from each other, and a second lead-out portion and a second dummy lead-out portion respectively extending from the second coil pattern, and respectively exposed to the first and second surfaces of the body, while being spaced apart from each other.
    Type: Application
    Filed: November 7, 2022
    Publication date: June 1, 2023
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Jun Ho Yoon
  • Patent number: 11658264
    Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 23, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Dae Hong Min, Jun Ho Yoon, Woo Cheol Gwak, Jin Woo Huh, Yong Hyun Baek
  • Patent number: 11244911
    Abstract: A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
  • Publication number: 20210366837
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Patent number: 11145601
    Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
  • Patent number: 11107773
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Publication number: 20210074883
    Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 11, 2021
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventors: Dae Hong MIN, Jun Ho YOON, Woo Cheol GWAK, Jin Woo HUH, Yong Hyun BAEK
  • Publication number: 20210057278
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10886234
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate which includes a semiconductor chip region and a scribe line region surrounding the semiconductor chip region; an insulating film arranged over the semiconductor chip region and the scribe line region on the substrate, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening portion formed on the second surface of the insulating film and the fourth surface of the insulating film to expose the substrate, wherein the opening portion is formed in the scribe line region, and the first surface of the insulating film and the third surface of the insulating film do not include an opening portion which expose the substrate.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jung Ho Choi
  • Patent number: 10854517
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10720491
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Won Chul Lee, Sung Yeon Kim, Jae Hong Park, Chan Hoon Park, Yong Moon Jang, Je Woo Han
  • Publication number: 20200221205
    Abstract: Disclosed herein is an in-ear earphone including a drum safety filter (DSF) path, the in-ear earphone including: an earcap; an acoustic structure; and an acoustic unit; wherein the acoustic structure and the acoustic unit include a DSF path configured to remove eardrum pressure during the use of the in-ear earphone by moving air across the front and rear sides of the in-ear earphone.
    Type: Application
    Filed: November 20, 2019
    Publication date: July 9, 2020
    Inventors: Minkoo PARK, Seungcheol LEE, Seungwoo CHUN, Jun Ho YOON
  • Publication number: 20200168556
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Application
    Filed: June 13, 2019
    Publication date: May 28, 2020
    Inventors: HYUN-SU SIM, YOON-SUNG KIM, YUN-HEE KIM, BYUNG-MOON BAE, JUN-HO YOON
  • Publication number: 20200126932
    Abstract: A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.
    Type: Application
    Filed: April 19, 2019
    Publication date: April 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yoon Sung KIM, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi