Abstract: An array substrate includes a slit electrode and a planar electrode disposed in each of sub-pixels on a base substrate. The planar electrode is located on a side of the slit electrode close to the base substrate, and the slit electrode includes a plurality of strip sub-electrodes. In each of the sub-pixels, an insulating layer is disposed between the slit electrode and the planar electrode, and a surface of the insulating layer facing away from the base substrate is provided with a groove at a position between at least one set of adjacent strip sub-electrodes in the plurality of strip sub-electrodes.

Abstract: An array substrate and a display device including the array substrate are provided. The array substrate includes: an upper electrode layer on a base substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer between the base substrate and the upper electrode layer. The lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate. The array substrate includes a pixel electrode strip and a common electrode strip which are in a same layer and both correspond to a region between the first upper electrode strip and the second upper electrode strip.

Abstract: A display panel includes a first display sub-panel and a second display sub-panel disposed opposite to each other, the first display sub-panel including a plurality of first gate lines and the second display sub-panel including a plurality of second gate lines. The display panel further includes a plurality of single-way conducting switches, the first gate lines, the second gate lines and the single-way conducting switches being disposed in one-to-one correspondence, each of the single-way conducting switches having an input end which is electrically connected to the corresponding first gate line and an output end which is electrically connected to the corresponding second gate line, and each of the single-way conducting switches being unidirectionaly conducted from the corresponding first gate line to the corresponding second gate line.

Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate, signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the array substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Abstract: An array substrate and a display device including the array substrate are provided. The array substrate includes: an upper electrode layer on a base substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer between the base substrate and the upper electrode layer. The lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate. The array substrate includes a pixel electrode strip and a common electrode strip which are in a same layer and both correspond to a region between the first upper electrode strip and the second upper electrode strip.

Abstract: A privacy protection component, a display panel and display device comprising the privacy protection component, and an adjusting method of the privacy protection component. The privacy protection component comprising a privacy protection substrate and a plurality of support structures. The privacy protection substrate is provided with a plurality of first electrodes and a plurality of second electrodes arranged in an array and distributed alternately. The plurality of support structures are hollow and filled with liquid crystals, and the plurality of support structures are located on the plurality of first electrodes respectively and extend away from the privacy protection substrate.

Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate; signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the arm substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Abstract: A display panel includes a first display sub-panel and a second display sub-panel disposed opposite to each other, the first display sub-panel including a plurality of first gate lines and the second display sub-panel including a plurality of second gate lines. The display panel further includes a plurality of single-way conducting switches, the first gate lines, the second gate lines and the single-way conducting switches being disposed in one-to-one correspondence, each of the single-way conducting switches having an input end which is electrically connected to the corresponding first gate line and an output end which is electrically connected to the corresponding second gate line, and each of the single-way conducting switches being unidirectionaly conducted from the corresponding first gate line to the corresponding second gate line.