Abstract: Disclosed in the present disclosure is a cross-band passive backscatter circuit, which belongs to the technical field of radio frequency transceivers. The cross-band passive backscatter circuit includes: an uplink including an input radio frequency antenna, a matching network, a carrier enhancement circuit, a carrier frequency division circuit, a cross-frequency backscatter module, a digital baseband, and an output reflection antenna; a power management unit including a rectifier, a bandgap reference, and a linear voltage regulator; and a downlink including a downlink demodulation circuit. In the present disclosure, frequency division output of a high-frequency carrier obtained by an on-chip low-power frequency divider and a high-frequency carrier are utilized to complete cross-band higher-frequency backscatter.

Abstract: Disclosed is a power supply assembly comprising a first printed circuit board (PCB), a second PCB that is vertically spaced apart from the first PCB, and a switch supported on the second PCB. The power supply assembly further comprises a conductive pillar that couples the first PCB to the second PCB, wherein current output by the switch flows from the switch to the first PCB via the conductive pillar.

Abstract: Disclosed in the present disclosure is a cross-band passive backscatter circuit, which belongs to the technical field of radio frequency transceivers. The cross-band passive backscatter circuit includes: an uplink including an input radio frequency antenna, a matching network, a carrier enhancement circuit, a carrier frequency division circuit, a cross-frequency backscatter module, a digital baseband, and an output reflection antenna; a power management unit including a rectifier, a bandgap reference, and a linear voltage regulator; and a downlink including a downlink demodulation circuit. In the present disclosure, frequency division output of a high-frequency carrier obtained by an on-chip low-power frequency divider and a high-frequency carrier are utilized to complete cross-band higher-frequency backscatter.

Abstract: The provided is a device and construction method for automatically placing a high-speed railway steel rail laying tie plate. The device includes a walking device, clamping devices and a plate dispersing device; the plate dispersing device is connected to a rear of the walking device; the clamping devices are arranged at two sides of the walking device; and the walking device and the plate dispersing device are both arranged on the rail plate, and a walking route of the walking device is parallel to the rail plate. Also provided is a construction method, including specific steps: arranging a walking device and a plate dispersing device; assembling a clamping device, clamping a clamping groove, adjusting a clamping arm adjusting bolt, and then tightening a locking nut; connecting the plate dispersing device to a frame; turning on the walking device, controlling a walking direction of the walking device, and dispersing plates.

Abstract: A pointing device is provided. In one implementation, the pointing device includes a body, a control member received in a recess of the body and rotatable with respect to the body, a first rotation tracking sensor arranged in the recess and configured to track a rotation of the control member about a first axis and a second axis perpendicular to the first axis in a Cartesian coordinate system that is defined with respect to the recess, and a second rotation tracking sensor arranged in the recess and configured to track a rotation of the control member about a third axis perpendicular to the first and second axes in the Cartesian coordinate system. An associated method of manufacturing the pointing device is also provided.

Abstract: The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.

Abstract: The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.

Abstract: The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.

Abstract: The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.