Patents by Inventor Junhua Luo
Junhua Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10005675Abstract: The present invention relates to the field of nonlinear optical crystal materials and provided herein a Li4Sr(BO3)2 compound, a Li4Sr(BO3)2 nonlinear optical crystal as well as preparation method and use thereof. The Li4Sr(BO3)2 nonlinear optical crystal has a second harmonic conversion efficiency at 1064 nm of about two times that of a KH2PO4 (KDP) crystal, and an UV absorption cut-off edge less than 190 nm. Furthermore, the crystal did not disintegrate. By flux method with Li2O, Li2O—B2O and Li2O—B2O3—LiF used as flux agent, large-size and transparent Li4Sr(BO3)2 nonlinear optical crystal can grow. The Li4Sr(BO3)2 crystal had stable physicochemical properties, moderate hardness, and was easy to cut, processing, preserve and use. Therefore it can be used for preparing nonlinear optical devices and thus for developing nonlinear optical applications in the ultraviolet and deep-ultraviolet band.Type: GrantFiled: June 20, 2013Date of Patent: June 26, 2018Assignees: ECHNICAL INSTITUTE OF PHYSICS AND CHEMISTRY, CHINESE ACADEMY OF SCIENCES, FUJIAN INSITUTE OF RESEARCH ON THE STRUCTURE OF MATTER, CHINESE ACADEMY OF SCIENCESInventors: Guochun Zhang, Junhua Luo, Mingjun Xia, Sangen Zhao, Yicheng Wu
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Publication number: 20160137515Abstract: The present invention relates to the field of nonlinear optical crystal materials and provided herein a Li4Sr(BO3)2 compound, a Li4Sr(BO3)2 nonlinear optical crystal as well as preparation method and use thereof. The Li4Sr(BO3)2 nonlinear optical crystal has a second harmonic conversion efficiency at 1064 nm of about two times that of a KH2PO4 (KDP) crystal, and an UV absorption cut-off edge less than 190 nm. Furthermore, the crystal did not disintegrate. By flux method with Li2O, Li2O-B2O and Li2O-B2O3-LiF used as flux agent, large-size and transparent Li4Sr(BO3)2 nonlinear optical crystal can grow. The Li4Sr(BO3)2 crystal had stable physicochemical properties, moderate hardness, and was easy to cut, processing, preserve and use. Therefore it can be used for preparing nonlinear optical devices and thus for developing nonlinear optical applications in the ultraviolet and deep-ultraviolet band.Type: ApplicationFiled: June 20, 2013Publication date: May 19, 2016Inventors: Guochun ZHANG, Junhua LUO, Mingjun XIA, Sangen ZHAO, Yicheng WU
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Patent number: 9093438Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.Type: GrantFiled: August 14, 2014Date of Patent: July 28, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Baoguan Yin, Junhua Luo, Deguo Sun
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Publication number: 20140357023Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.Type: ApplicationFiled: August 14, 2014Publication date: December 4, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Baoguan Yin, Junhua Luo, Deguo Sun
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Patent number: 8859336Abstract: A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.Type: GrantFiled: February 16, 2012Date of Patent: October 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Junhua Luo, Zhigang Bai, Nan Xu, Jinzhong Yao
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Publication number: 20140284806Abstract: A semiconductor device has first and semiconductor dies having active faces presenting electrical contact elements and back faces attached to first and second bonding areas side by side on an electrically conductive die support. A layer of electrically insulating material is applied to the first bonding area of the die support. A layer of electrically insulating adhesive bonding material attaches the back face of the first semiconductor die to the first bonding area of the die support through the layer of electrically insulating material. A layer of electrically conductive adhesive bonding material attaches the back face of the second semiconductor die to the second bonding area of the die support.Type: ApplicationFiled: February 18, 2014Publication date: September 25, 2014Inventors: Junhua Luo, Nan Xu, Jinzhong Yao
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Patent number: 8836105Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.Type: GrantFiled: November 20, 2012Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Baoguan Yin, Junhua Luo, Deguo Sun
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Patent number: 8722465Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.Type: GrantFiled: January 14, 2014Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Junhua Luo, Jinzhong Yao, Baoguan Yin
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Publication number: 20140127862Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Inventors: Junhua Luo, Jinzhong Yao, Baoguan Yin
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Patent number: 8643170Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.Type: GrantFiled: April 10, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Junhua Luo, Jinzhong Yao, Baoguan Yin
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Publication number: 20140027896Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.Type: ApplicationFiled: November 20, 2012Publication date: January 30, 2014Inventors: Baoguan Yin, Junhua Luo, Deguo Sun
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Patent number: 8481369Abstract: A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices.Type: GrantFiled: January 11, 2011Date of Patent: July 9, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Junhua Luo, Xingshou Pang, Jinzhong Yao
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Publication number: 20130037966Abstract: A semiconductor device includes a semiconductor die having first and second opposing faces and an edge surface. The edge surface has an undercut under the first face. The second face of the semiconductor die is bonded to a bonding surface of a die support member, such as a thermally conductive flag of a lead frame, with a die attach material. A fillet of the bonding material is formed within the undercut.Type: ApplicationFiled: June 13, 2012Publication date: February 14, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Shunan QIU, Guoliang Gong, Junhua Luo, Xuesong Xu
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Publication number: 20120264258Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.Type: ApplicationFiled: April 10, 2012Publication date: October 18, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Junhua LUO, Jinzhong Yao, Baoguan Yin
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Publication number: 20120238058Abstract: A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.Type: ApplicationFiled: February 16, 2012Publication date: September 20, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Junhua LUO, Zhigang BAI, Nan XU, Jinzhong YAO
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Publication number: 20110189823Abstract: A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices.Type: ApplicationFiled: January 11, 2011Publication date: August 4, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Junhua Luo, Xingshou Pang, Jinzhong Yao
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Publication number: 20100283135Abstract: A lead frame including a lead frame structure having a die support area and a plurality of electrical contact areas has shallow recesses formed on a surface of the lead frame structure.Type: ApplicationFiled: April 2, 2010Publication date: November 11, 2010Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Jinzhong YAO, Zhigang Bai, Junhua Luo, Meijiang Song, Hong Zhu
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Publication number: 20090249312Abstract: An approach for process generation for computer telephony integration (CTI) of an integrated telecom platform, including the following steps. Step 1: The process input module receives the flow chart input by a user and saves it as a flow chart record file; Step 2: the process coversion module coverts the flow chart record file into the equivalent source codes and saves them as a flow chart coversion output file; Step 3: the process compilation module compiles the flow chart coversion output file and saves it as a flow chart compilation output file. The invention also announces a process generation system for an integrated telecom platform, including the process input module, the process coversion module and the process compilation module. The invention is an ideal system for various CTI applications, allowing easy and fast subsequent development as well as convenient system upgrade and maintenance.Type: ApplicationFiled: June 9, 2006Publication date: October 1, 2009Applicant: SHENZHEN DONJIN COMMUNICATION TECH CO., LTD.Inventors: Yongkun Liao, Junhua Luo, Wei He