Abstract: A height-adjustable desk includes a base, a desk board assembly, a support arm assembly and a supporter. The desk board assembly is above the base, and the support arm assembly is a rhombic linkage mechanism. The support arm assembly includes a first arm segment, a second arm segment, a third arm segment and a fourth arm segment. Bottom ends of the first and second arm segments rotatably connect with the base, and top ends of the third and fourth arm segments rotatably connect with the desk board assembly. A top end of the first arm segment rotatably connects with a bottom end of the third arm segment, and a top end of the second arm segment rotatably connects with a bottom end of the fourth arm segment. The first and second arm segments, and the third and fourth arm segments connect in an engaging transmission manner, respectively.

Abstract: Disclosed is an energy storage and steam generation system, including an electrode steam boiler. One side of the electrode steam boiler is connected with a boiler deaerator through a pipeline. A pipeline A is arranged at the top of the electrode steam boiler. The pipeline A is connected with a steam superheater, and an outlet of the steam superheater is provided with an external steam supply outlet pipeline. A molten salt steam generation bypass pipeline and a pipeline B are arranged on the steam superheater. One end of the molten salt steam generation bypass pipeline is connected to the steam superheater. A low-temperature molten salt storage tank is connected to the pipeline B, and a high-temperature molten salt storage tank is connected to the low-temperature molten salt storage tank through a pipeline. The other end of the molten salt steam generation bypass pipeline is connected to the high-temperature molten salt storage tank. Meanwhile, a generation method is further disclosed.

Abstract: Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Abstract: A laser pulse emitter circuit comprises a laser diode and a laser diode driver circuit. The laser diode driver circuit includes an inductive circuit element in series with the laser diode, at least one capacitive circuit element connected in series with the inductive circuit element, and a switch circuit configured to activate the laser diode using duty cycling that includes an on-period and an off-period, wherein energy used in an activation of the laser diode is stored in the inductive circuit element and the at least one capacitive circuit element, and the stored energy is recycled by use in a subsequent activation of the laser diode.

Abstract: A time-of-flight (ToF) transmitter with self-stabilized optical output phase with minimal overhead is described, where the transmitter may either function as a slave in that the laser pulse phase and width can be controlled by the master ToF receiver, or it can function as a master where the laser control pulse is generated on the same chip or a companion chip. When the ToF transmitter functions as a slave and receives the laser pulse control signal, the techniques of this disclosure can transform the receive path and the pre-driver circuit into part of a delay locked loop (DLL).

Abstract: Monitoring temperature of a laser diode and adjusting usage of the laser diode based on the monitoring information. The method of monitoring includes using a laser driver circuit to drive the laser diode to deliver multiple test current stimuli at different times related to the laser driver issuing one or a burst of illumination pulses. A differential measurement can be made between at least two of the test current stimuli. The differential measurement can be used to determine an indication of the heating or health of the laser diode in the system or of the laser system as a whole.

Abstract: Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Abstract: A laser emitter circuit comprises a laser diode; a driver circuit configured to generate a drive signal; and a resonant circuit coupled to the driver circuit and the laser diode, wherein the resonant circuit is configured to use the drive signal of the driver circuit to generate a continuous wave sinusoidal drive signal to drive the laser diode.

Abstract: A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element.

Abstract: A laser emitter circuit comprises a laser diode; a driver circuit configured to generate a drive signal; and a resonant circuit coupled to the driver circuit and the laser diode, wherein the resonant circuit is configured to use the drive signal of the driver circuit to generate a continuous wave sinusoidal drive signal to drive the laser diode.

Abstract: A communication method for a mobile terminal and a mobile terminal, where the communication method includes detecting whether the mobile terminal uses a call service, obtaining a state of an access control circuit when the mobile terminal uses the call service, and selecting a process of network quality monitoring based on the obtained state of the access control circuit, where the process of network quality monitoring includes stopping network quality monitoring, or stopping reporting a network quality monitoring result to a network side. Hence, the network side can process the call service of the mobile terminal based on the process of network quality monitoring performed by the mobile terminal to avoid a before-ringing inter-system handover and improve user experience.

Abstract: A laser pulse emitter circuit comprises a laser diode and a laser diode driver circuit. The laser diode driver circuit includes an inductive circuit element in series with the laser diode, at least one capacitive circuit element connected in series with the inductive circuit element, and a switch circuit configured to activate the laser diode using duty cycling that includes an on-period and an off-period, wherein energy used in an activation of the laser diode is stored in the inductive circuit element and the at least one capacitive circuit element, and the stored energy is recycled by use in a subsequent activation of the laser diode.

Abstract: A time-of-flight (ToF) transmitter with self-stabilized optical output phase with minimal overhead is described, where the transmitter may either function as a slave in that the laser pulse phase and width can be controlled by the master ToF receiver, or it can function as a master where the laser control pulse is generated on the same chip or a companion chip. When the ToF transmitter functions as a slave and receives the laser pulse control signal, the techniques of this disclosure can transform the receive path and the pre-driver circuit into part of a delay locked loop (DLL).

Abstract: A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element.

Abstract: A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).

Abstract: A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.

Abstract: A communication method for a mobile terminal and a mobile terminal, where the communication method includes detecting whether the mobile terminal uses a call service, obtaining a state of an access control circuit when the mobile terminal uses the call service, and selecting a process of network quality monitoring based on the obtained state of the access control circuit, where the process of network quality monitoring includes stopping network quality monitoring, or stopping reporting a network quality monitoring result to a network side. Hence, the network side can process the call service of the mobile terminal based on the process of network quality monitoring performed by the mobile terminal to avoid a before-ringing inter-system handover and improve user experience.

Abstract: A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.

Abstract: Improvements in analog-to-digital converter (ADC) circuit accuracy are described that can utilize a digital-to-analog converter (DAC) circuit with one or more redundant unit elements, or one or more bits redundancy or non-binary weighted capacitors, and can reuse the existing DAC circuit for noise reduction to save power and die area. An ADC circuit can use redundancy bit(s), e.g., one or more DAC unit elements of a main DAC, and the remaining lower bits of the main DAC for repeated bit trials, and can average the data from the repeated bit trials to suppress noise from conversions.

Abstract: A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.