Abstract: A fractional-N phase locked loop (PLL) is described and includes a synchronized feed forward frequency decoder configured to generate a VCO frequency code from a feedback divider ratio and an update rate input thereto; and a scalable voltage-controlled oscillator (VCO) comprising an array of ring cells, wherein each of the ring cells comprises a multi-stage ring VCO comprising a plurality of inverters, wherein a transconductance of each of the ring cells is controlled by bias voltage signals applied to a selected one of the ring cells.

Abstract: A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.

Abstract: A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.