Abstract: The present application provides a method and a structure for improving ESD performance of a metal-gate high-voltage device, wherein a first STI region and a second STI region are formed within the high voltage P-well; a first high-voltage region N-diffusion region is formed within the high voltage P-well between the first STI region and second STI region; the area immediately adjacent to the first STI region and the area immediately adjacent to the second STI region are filled with silicon oxide; the silicon oxide immediately adjacent to the first STI region is formed as a first silicon oxide structure, and the silicon oxide immediately adjacent to the second STI region is formed as a second silicon oxide structure; and an IO N-well is formed within the first high-voltage region N-diffusion region of the lower area between the first silicon oxide structure and second silicon oxide structure.

Abstract: A level shift circuit comprises a pull-down circuit which includes a first sub-circuit and a second sub-circuit connected in series. A control end of the first sub-circuit is connected to a bias voltage. A first end of the first sub-circuit is connected to a high-voltage output end, and a second end is connected to a first end of the second sub-circuit. A second end of the second sub-circuit is connected to the ground and a control end provides a low-voltage input end. The voltage at the second end of the first sub-circuit changes with the bias voltage. The magnitude of the bias voltage is set such that the first sub-circuit is kept in a conducted state and the maximum voltage at the second end of the first sub-circuit is lower than or equal to the withstand voltage of the second sub-circuit.