Abstract: An instruction transmission method is performed by an instruction decode unit of a processor, which obtains transmission states of two transmission channels in a transmission period; according to a combination of the transmission states of the two transmission channels, generates a transmission control signal for the two transmission channels; and controls, according to the transmission control signal, the two transmission channels to transmit instructions to an execution unit.

Abstract: A neural network processing method, a neural network processing unit (NPU) and a processing device are provided. The method includes: obtaining by a quantizing unit in the NPU float type input data, quantizing the float type input data to obtain quantized input data, and providing the quantized input data to an operation unit; performing by the operation unit of the NPU a matrix-vector operation and/or a convolution operation to the quantized input data to obtain an operation result of the quantized input data; and performing by the quantizing unit inverse quantization to the operation result output by the operation unit to obtain an inverse quantization result.

Abstract: The present application discloses a processing method, device, equipment and storage medium of a loop instruction, and relates to the fields of voice and chips. A specific embodiment is: acquiring a computer program including a first loop body, where the first loop body is generated according to a second loop body in a software code to be compiled, the first loop body includes a plurality of first loop instructions, the plurality of first loop instructions can be identified by a hardware structure of a computer device; in the case that the first loop body is detected, determining loop parameters of the first loop body according to the plurality of first loop instructions; acquiring the plurality of first loop instructions according to the loop parameters of the first loop body; executing the plurality of first loop instructions.

Abstract: A data processing method for a neural network accelerator, an electronic device and a storage medium are provided. The technical solution includes: obtaining data to be processed and an operation to be executed; obtaining a real-number full-connection operation corresponding to the operation to be executed; and performing the real-number full-connection operation on the data based on a real-number full-connection unit of the neural network accelerator to obtain a result of the operation to be executed for the data.

Abstract: The present application discloses a voice processing system and method, an electronic device and a readable storage medium, which relates to the field of voice processing technologies. The voice processing system includes: a neural-network processing unit (NPU) and an RISC-V processor; wherein the RISC-V processor includes predefined NPU instructions, and the RISC-V processor is configured to send the NPU instructions to the NPU to cause the NPU to perform corresponding neural network computation; the NPU includes a memory unit and a computing unit, and the memory unit includes a plurality of storage groups; the computing unit is configured to execute one of main computation, special computation, auxiliary computation and complex instruction set computing (CISC) control according to the received NPU instructions.

Abstract: The present application discloses a memory control method, a controller, a chip and an electronic device, and relates to the field of control technology. A specific implementation solution is: obtaining first address information of an access to the memory performed by the processor within a first time window; determining, according to the first address information and an address jump relationship, a target slice of the memory that is to be accessed by the processor within a second time window; and controlling the target slice in the memory to be turned on and controlling a slice other than the target slice in the memory to be turned off within the second time window. Through the above-mentioned process, each slice is dynamically turned on and off according to the actual situation of memory access, thereby reducing the power consumption of the memory to the maximum extent.

Abstract: The present application discloses a processing method, device, equipment and storage medium of a loop instruction, and relates to the fields of voice and chips. A specific embodiment is: acquiring a computer program including a first loop body, where the first loop body is generated according to a second loop body in a software code to be compiled, the first loop body includes a plurality of first loop instructions, the plurality of first loop instructions can be identified by a hardware structure of a computer device; in the case that the first loop body is detected, determining loop parameters of the first loop body according to the plurality of first loop instructions; acquiring the plurality of first loop instructions according to the loop parameters of the first loop body; executing the plurality of first loop instructions.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for processing information. The method may include: determining an instruction category of an instruction based on an instruction operation code of the acquired instruction, where the instruction category includes a dedicated instruction including register selection information, base address information, and a length of to-be-read data; sending, in response to determining that the instruction is the dedicated instruction, the dedicated instruction to a preset operator for the operator to perform following operation steps: selecting a configuration register group from preset configuration register groups as a target configuration register group according to the register selection information; reading configuration information from the target configuration register group based on the base address information and the length of the to-be-read data; performing a preset operation for the configuration information.

Abstract: The present application discloses a memory control method, a controller, a chip and an electronic device, and relates to the field of control technology. A specific implementation solution is: obtaining first address information of an access to the memory performed by the processor within a first time window; determining, according to the first address information and an address jump relationship, a target slice of the memory that is to be accessed by the processor within a second time window; and controlling the target slice in the memory to be turned on and controlling a slice other than the target slice in the memory to be turned off within the second time window. Through the above-mentioned process, each slice is dynamically turned on and off according to the actual situation of memory access, thereby reducing the power consumption of the memory to the maximum extent.