Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: Provided are semiconductor devices including device isolation layers. The semiconductor device includes a substrate having a cell region and a core/peripheral region, a first active region in the cell region of the substrate, a first device isolation layer that defines the first active region, a second active region in the core/peripheral region of the substrate; and a second device isolation layer that defines the second active region. A height from a lower surface of the substrate to an upper end of the first device isolation layer in a first direction that is perpendicular to the lower surface of the substrate is less than or equal to a height from the lower surface of the substrate to an upper end of the first active region in the first direction.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.