Abstract: A regulator circuit includes an operational amplifier, a buffer, a power transistor, a first feedback circuit, a current sensor, and second feedback circuit. The operational amplifier drives a first node with a first voltage generated by amplifying a difference between an input voltage and a feedback voltage. The buffer drives a second node with a second voltage generated by buffering the first voltage. The power transistor has a drain receiving a supply voltage, a gate connected to the second node, and a source connected to a third node. The current sensor generates a first sensing current based on the second voltage. The second feedback circuit generates a plurality of feedback currents corresponding to a ripple of the output voltage and enhances a speed at which the ripple is reduced by providing at least one of the plurality of feedback currents to the third node.

Abstract: A regulator circuit includes an operational amplifier, a buffer, a power transistor, a first feedback circuit, a current sensor, and second feedback circuit. The operational amplifier drives a first node with a first voltage generated by amplifying a difference between an input voltage and a feedback voltage. The buffer drives a second node with a second voltage generated by buffering the first voltage. The power transistor has a drain receiving a supply voltage, a gate connected to the second node, and a source connected to a third node. The current sensor generates a first sensing current based on the second voltage. The second feedback circuit generates a plurality of feedback currents corresponding to a ripple of the output voltage and enhances a speed at which the ripple is reduced by providing at least one of the plurality of feedback currents to the third node.

Abstract: A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.

Abstract: A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.

Abstract: Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal.

Abstract: A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.

Abstract: A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.