Patents by Inventor Junich Sugiyama

Junich Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIFO memory device capable of writing contiguous data into rows
    Patent number: 5521876
    Abstract: A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage units cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: May 28, 1996
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Hattori, Junich Sugiyama
  • FIFO memory device capable of writing contiguous data into rows
    Patent number: 5515330
    Abstract: A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage unit cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: May 7, 1996
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Hattori, Junich Sugiyama
  • FIFO memory device capable of writing contiguous data into rows
    Patent number: 5513145
    Abstract: A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage unit cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: April 30, 1996
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Hattori, Junich Sugiyama
  • FIFO memory device capable of writing contiguous data into rows
    Patent number: 5412611
    Abstract: A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage unit cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: May 2, 1995
    Assignee: Fujitsu, Limited
    Inventors: Hiroshi Hattori, Junich Sugiyama