Patents by Inventor Junichi Asada

Junichi Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9911449
    Abstract: The first, third, fourth, and seventh photosensors are disposed on one side with respect to the centerline, and the second, fifth, sixth, and eighth photosensors are disposed on another side with respect to the centerline. The first and seventh photosensors are positioned between the third and fourth photosensors in the direction parallel to the centerline. The second and eighth photosensors are positioned between the fifth and sixth photosensors in the direction parallel to the centerline. The first photosensor receives overlapped light of the 0th-order light with the +1st-order diffracted light, the second photosensor receives overlapped light of the 0th-order light with the ?1st-order diffracted light, each of the third to sixth photosensors receives the 0th-order light, and does not receive the +1st-order diffracted light and the ?1st-order diffracted light, and each of the seventh and eighth photosensors receives at least the 0th-order light.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 6, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuo Momoo, Junichi Asada, Yasushi Kobayashi, Kousei Sano, Yuichi Takahashi
  • Patent number: 9870507
    Abstract: In the image extraction device, an instruction acquisition unit acquires an instruction input by a user, and an image group selection unit selects a second image group, which has a smaller number of images than a first image group, from the first image group in response to the instruction. Then, an extraction reference determination unit determines an image extraction reference when extracting an image from the second image group based on images included in the first image group, and an image extraction unit extracts one or more images, the number of which is smaller than the number of images in the second image group, from the second image group according to the image extraction reference.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: January 16, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Kei Yamaji, Junichi Asada
  • Publication number: 20170263280
    Abstract: The first, third, fourth, and seventh photosensors are disposed on one side with respect to the centerline, and the second, fifth, sixth, and eighth photosensors are disposed on another side with respect to the centerline. The first and seventh photosensors are positioned between the third and fourth photosensors in the direction parallel to the centerline. The second and eighth photosensors are positioned between the fifth and sixth photosensors in the direction parallel to the centerline. The first photosensor receives overlapped light of the 0th-order light with the +1st-order diffracted light, the second photosensor receives overlapped light of the 0th-order light with the ?1st-order diffracted light, each of the third to sixth photosensors receives the 0th-order light, and does not receive the +1st-order diffracted light and the ?1st-order diffracted light, and each of the seventh and eighth photosensors receives at least the 0th-order light.
    Type: Application
    Filed: December 13, 2016
    Publication date: September 14, 2017
    Inventors: Kazuo MOMOO, Junichi ASADA, Yasushi KOBAYASHI, Kousei SANO, Yuichi TAKAHASHI
  • Publication number: 20170070620
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a case, a memory in the case, a controller in the case. The controller controls the memory. First information including a determination code is printed on a surface of the case with invisible ink. Second information related to the nonvolatile semiconductor memory device is printed with visible ink which is visually recognizable in a visible light range.
    Type: Application
    Filed: February 5, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinya OHASHI, Junichi ASADA, ltaru MORI
  • Publication number: 20160371536
    Abstract: In the image extraction device, an instruction acquisition unit acquires an instruction input by a user, and an image group selection unit selects a second image group, which has a smaller number of images than a first image group, from the first image group in response to the instruction. Then, an extraction reference determination unit determines an image extraction reference when extracting an image from the second image group based on images included in the first image group, and an image extraction unit extracts one or more images, the number of which is smaller than the number of images in the second image group, from the second image group according to the image extraction reference.
    Type: Application
    Filed: April 22, 2016
    Publication date: December 22, 2016
    Applicant: FUJIFILM Corporation
    Inventors: Kei YAMAJI, Junichi ASADA
  • Patent number: 9347620
    Abstract: According to one embodiment, a semiconductor device includes a board, a controller chip, a semiconductor chip, a sealing portion, and a component. The board includes a first surface and a second surface opposite to the first surface, the first surface comprising a terminal. The controller chip is on the second surface of the board. The semiconductor chip is on the second surface of the board. The sealing portion integrally covers the controller chip and the semiconductor chip and does not cover a region of the second surface of the board. The component is on the region of the second surface of the board to perform an operation with respect to the outside of the semiconductor device.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 24, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki Kogure, Yuuta Yamada, Takeshi Ikuta, Toshiyuki Hayakawa, Junichi Asada
  • Publication number: 20160077555
    Abstract: According to one embodiment, a USB memory device includes: a substrate including a semiconductor chip, a plurality of operating terminals, a reference potential terminal and a reference potential wiring; and a housing holding the substrate inside, being electrically connected to the reference potential terminal, and having electric conductivity. The reference potential wiring electrically connects the operating terminal with the reference potential terminal.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 17, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuuta YAMADA, Takeshi MITSUHASHI, Junichi ASADA
  • Publication number: 20150254545
    Abstract: According to one embodiment, a memory card includes a housing and a switch. The housing includes a first surface and a second surface. The second surface is opposite to the first surface. The switch includes a first part, a second part, and a third part. The first part is disposed outside from the housing. The third part is disposed in the housing. The second part is connected to both the first part and the third part. The third part is in contact with both the first surface and the second surface.
    Type: Application
    Filed: August 26, 2014
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hironari UEHARA, Akihiro IIDA, Junichi ASADA
  • Publication number: 20150043228
    Abstract: According to one embodiment, a semiconductor device includes a board, a controller chip, a semiconductor chip, a sealing portion, and a component. The board includes a first surface and a second surface opposite to the first surface, the first surface comprising a terminal. The controller chip is on the second surface of the board. The semiconductor chip is on the second surface of the board. The sealing portion integrally covers the controller chip and the semiconductor chip and does not cover a region of the second surface of the board. The component is on the region of the second surface of the board to perform an operation with respect to the outside of the semiconductor device.
    Type: Application
    Filed: January 9, 2014
    Publication date: February 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki KOGURE, Yuuta YAMADA, Takeshi IKUTA, Toshiyuki HAYAKAWA, Junichi ASADA
  • Publication number: 20140287605
    Abstract: According to one embodiment, a semiconductor device includes a case, a connector, and a cap. The case includes a first main surface, a second main surface opposite to the first main surface, a first concave portion provided with at least one of the first main surface and the second main surface, and a semiconductor memory housed inside. The connector is connected to the case. The cap includes a third main surface, a fourth main surface opposite to the third main surface, a locking portion provided with at least one of the third main surface and the fourth main surface which is locked with the first concave portion, and a side surface provided with an opening portion opening between the third main surface and the fourth main surface.
    Type: Application
    Filed: December 27, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuta YAMADA, Junichi Asada
  • Patent number: 8797834
    Abstract: A disclosed objective lens includes: a lens having an entrance surface and an emission surface; and an anti-reflection coat formed on the emission surface, wherein a transmittance T1—0 [%] of the anti-reflection coat when an incident angle of a first laser beam having a first wavelength ?1 (390 nm??1?430 nm) is 0°, and the transmittance T1—40 [%] of the anti-reflection coat when the incident angle of the first laser beam is 40° satisfy 0.95?T1—0/T1—40?1.05, and a transmittance T2—0 [%] of the anti-reflection coat when an incident angle of a second laser beam having a second wavelength ?2 (630 nm??2?680 nm) is 0° and a transmittance T2—40 [%] of the anti-reflection coat when the incident angle of the second laser beam is 40° satisfy 0.85?T2—0/T2—40?0.97.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: August 5, 2014
    Assignee: Panasonic Corporation
    Inventors: Fumitomo Yamasaki, Hiroshi Shiroiwa, Yoshiaki Komma, Junichi Asada, Osamu Kajino, Noriaki Terahara, Toshiyasu Tanaka
  • Patent number: 8581372
    Abstract: According to one embodiment, a semiconductor storage device includes a plate and an external connection terminal. The plate is molded in a resin mold section. A semiconductor memory chip is placed on the plate. The external connection terminal is exposed to the outer circumferential surface of the semiconductor storage device. The plate includes a plurality of exposed portions exposed to the outer circumferential surface of the resin mold section. The plurality of exposed portions is electrically insulated from each other inside the resin mold section.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Asada, Taku Nishiyama, Atsuko Seki
  • Patent number: 8432782
    Abstract: An objective lens, an optical head, an optical disk apparatus and an information processing apparatus which can suppress deterioration of a focal spot caused by a drop in the diffraction efficiency. Inner and outer circumference areas converge a laser beam, out of laser beams having a wavelength ?1 which are diffracted by the inner and outer circumference areas, on a first information recording medium; the inner circumference area and a mid-circumference area converge a laser beam, out of the laser beams having a wavelength ?2 which are diffracted by the inner circumference area and the mid-circumference area, on a second information recording medium; and the diffraction efficiency of the laser beam having the wavelength ?2 is greater than the diffraction efficiency of the laser beam having the wavelength ?1.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: April 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Fumitomo Yamasaki, Kazuhiro Minami, Yoshiaki Komma, Junichi Asada, Osamu Kajino, Noriaki Terahara, Toshiyasu Tanaka
  • Publication number: 20130064057
    Abstract: A disclosed objective lens includes: a lens having an entrance surface and an emission surface; and an anti-reflection coat formed on the emission surface, wherein a transmittance T1—0 [%] of the anti-reflection coat when an incident angle of a first laser beam having a first wavelength ?1 (390 nm??1?430 nm) is 0°, and the transmittance T1—40 [%] of the anti-reflection coat when the incident angle of the first laser beam is 40° satisfy 0.95?T1—0/T1—40?1.05, and a transmittance T2—0 [%] of the anti-reflection coat when an incident angle of a second laser beam having a second wavelength ?2 (630 nm??2?680 nm) is 0° and a transmittance T2—40 [%] of the anti-reflection coat when the incident angle of the second laser beam is 40° satisfy 0.85?T2—0/T2—40?0.97.
    Type: Application
    Filed: May 31, 2011
    Publication date: March 14, 2013
    Inventors: Fumitomo Yamasaki, Hiroshi Shiroiwa, Yoshiaki Komma, Junichi Asada, Osamu Kajino, Noriaki Terahara, Toshiyasu Tanaka
  • Publication number: 20120182852
    Abstract: An objective lens, an optical head, an optical disk apparatus and an information processing apparatus which can suppress deterioration of a focal spot caused by a drop in the diffraction efficiency are provided.
    Type: Application
    Filed: July 22, 2011
    Publication date: July 19, 2012
    Inventors: Fumitomo Yamasaki, Kazuhiro Minami, Yoshiaki Komma, Junichi Asada, Osamu Kajino, Noriaki Terahara, Toshiyasu Tanaka
  • Publication number: 20120049378
    Abstract: According to one embodiment, a semiconductor storage device includes a plate and an external connection terminal. The plate is molded in a resin mold section. A semiconductor memory chip is placed on the plate. The external connection terminal is exposed to the outer circumferential surface of the semiconductor storage device. The plate includes a plurality of exposed portions exposed to the outer circumferential surface of the resin mold section. The plurality of exposed portions is electrically insulated from each other inside the resin mold section.
    Type: Application
    Filed: March 18, 2011
    Publication date: March 1, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Junichi Asada, Taku Nishiyama, Atsuko Seki
  • Patent number: 8045432
    Abstract: Light emitted from a radiation light source 1 passes through a diffraction grating 3a and is separated into transmitted light a and +1st/?1st order diffracted lights b, c. These lights are collected through an objective lens 7 on tracks of an optical disc 8 in a partially overlapped state. Light reflected by the tracks passes through the objective lens 7 and is incident upon light diverging means 13a. Subsequently, light corresponding to the transmitted light “a” diverges into two light beams that are respectively incident upon light detection regions A1, A2, light corresponding to the diffracted lights “b” and “c” respectively diverges into two light beams that are respectively incident upon light detection regions B1, B2, and C1, C2. A tracking error signal associated with the tracks of the optical disc 8 is generated by combining signals detected in the light detection regions A1, A2, B1, B2, C1, and C2.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiji Nishiwaki, Kazuo Momoo, Junichi Asada
  • Publication number: 20090279403
    Abstract: Light emitted from a radiation light source 1 passes through a diffraction grating 3a and is separated into transmitted light a, +1st order diffracted light b, and ?1st order diffracted light c. The transmitted light a, +1st order diffracted light b, and ?1st order diffracted light c are collected through an objective lens 7 on tracks on the signal plane 8a of an optical disc 8 in a partially overlapped state. Light reflected by the tracks on the signal plane 8a passes through the objective lens 7 and is incident upon light diverging means 13a.
    Type: Application
    Filed: March 19, 2007
    Publication date: November 12, 2009
    Applicant: Panasonic Corporation
    Inventors: Seiji Nishiwaki, Kazuo Momoo, Junichi Asada
  • Publication number: 20090028036
    Abstract: The invention permits stable tracking with few control errors, uninfluenced by stray light reflected by signal surfaces other than the signal surface being used for focusing during recording and playback of a multilayer disc. To this end, the optical splitter element of the optical disc device according to the present invention has first areas (21c-24c), which include the location (20) of the optical axis of light incident from the objective lens, and, around the periphery of the first areas, second areas (21a-24a, 21b-24b) positioned at locations displaced from the optical axis. The detection surface (9a) of the photodetector has first detection areas (97, 98) detecting light incident from the first areas and second detection areas (95, 96) detecting light incident from the second areas. The second detection areas are used for detecting tracking error signals.
    Type: Application
    Filed: March 13, 2007
    Publication date: January 29, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Seiji Nishiwaki, Kazuo Momoo, Junichi Asada
  • Patent number: 6987313
    Abstract: Disclosed is a semiconductor device constructed such that a lead wire extending from an interposer is connected to a pad of a chip, wherein the chip is bonded to a resin molding with a high mechanical strength. In the semiconductor device of the present invention, the lead wires extending from the interposer formed of a polyimide film are connected to the pad of the chip, and the lead wires are arranged sparse. Dummy lead wires irrelevant to the electrical connection are also arranged in addition to the lead wires extending from the interposer so as to increase the total number of lead wires supporting the chip so as to permit the chip 11 to be bonded to the resin molding 15 with a high mechanical strength. The dummy lead wires mounted to the interposer together with the lead wires serve to improve the bonding strength between the resin molding and the chip.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: January 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichi Asada