Patents by Inventor Junichi Fujikata

Junichi Fujikata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110012221
    Abstract: The lattice mismatching between a Ge layer and a Si layer is as large as about 4%. Thus, when the Ge layer is grown on the Si layer, penetration dislocation is introduced to cause leakage current at the p-i-n junction. Thereby, the photo-detection sensitivity is reduced, and the reliability of the element is also lowered. Further, in the connection with a Si waveguide, there are also problems of the reflection loss due to the difference in refractive index between Si and Ge, and of the absorption loss caused by a metal electrode.
    Type: Application
    Filed: March 9, 2009
    Publication date: January 20, 2011
    Inventors: Junichi Fujikata, Toru Tatsumi, Akihito Tanabe, Jun Ushida, Daisuke Okamoto, Kenichi Nishi
  • Publication number: 20110002582
    Abstract: Provided is a semiconductor optical interconnection device capable of transmitting signals between laminated semiconductor chips in a structure where semiconductor chips highly functionalized by being bonded to an optical interconnection chip are laminated. The semiconductor optical interconnection device includes a semiconductor chip 1 and an optical interconnection chip 2. The optical interconnection chip 2 includes an optical element formed thereon (for instance, a photo-sensitive element, a luminous element, or an optical modulator) which has a function relating to signal conversion between light and electricity. The semiconductor chip 1 includes a transmission section 3 (for instance, a coil or an inductor) to transmit signals in a non-contact manner, and a connection section 4 (for instance, a bump) to electrically connect with the optical element.
    Type: Application
    Filed: February 10, 2009
    Publication date: January 6, 2011
    Inventors: Daisuke Okamoto, Kenichi Nishi, Junichi Fujikata, Jun Ushida
  • Publication number: 20100327385
    Abstract: The Si waveguide 305 includes a first conductivity-type Si layer 301 and an intrinsic Si layer 302, and a second conductivity-type light-absorption layer 303 is partially formed on an area thereof. During operation, a reverse bias is applied between the first conductivity-type Si layer 301 and the light-absorption layer 303. Since the light-absorption layer 303 has a conductivity type, it is not depleted when a voltage is applied, but the intrinsic Si layer 302 forming the Si waveguide 305 is depleted. Therefore, it is possible to reduce a CR time constant. Furthermore, since the intrinsic Si layer 302 can be formed on the first conductivity-type Si layer 301 in a continuous manner, it is possible to reduce lattice defects. As a result, it is possible to suppress the dark current generated in the light-receiving element.
    Type: Application
    Filed: March 5, 2009
    Publication date: December 30, 2010
    Inventors: Kazuhiro Shiba, Junichi Fujikata
  • Publication number: 20100320496
    Abstract: A semiconductor device comprises a semiconductor layer having a semiconductor integrated circuit, which is for processing an electrical signal, on a semiconductor substrate and an optical interconnect layer for transmitting an optical signal are joined. Control of modulation of the optical signal transmitted in the optical interconnect layer is performed by an electrical signal from the semiconductor layer, and an electrical signal generated by reception of light in the optical interconnect layer is transmitted to the semiconductor layer. The optical interconnect layer is disposed on the underside of the semiconductor substrate.
    Type: Application
    Filed: February 26, 2009
    Publication date: December 23, 2010
    Inventors: Kenichi Nishi, Junichi Fujikata, Jun Ushida, Daisuke Okamoto
  • Publication number: 20100316325
    Abstract: Provided is a small-size optical phase modulation element and an optical modulator using it. The optical phase modulation element includes a Plasmon waveguide having a clad made of a metal material having a complex dielectric constant having a negative real part in the used wavelength and a core formed by a dielectric metal material having a complex dielectric constant having a positive real part in the used wavelength. The Plasmon waveguide is connected to an optical waveguide including a clad and a core both having a complex dielectric constant having a positive real part. The core of the Plasmon waveguide and the core of the optical waveguide are formed, at least partially, of the same semiconductor material. The Plasmon waveguide has a function to phase-modulate the incident light when voltage is applied.
    Type: Application
    Filed: December 25, 2007
    Publication date: December 16, 2010
    Inventors: Daisuke Okamoto, Masafumi Nakada, Junichi Fujikata
  • Publication number: 20100308428
    Abstract: A semiconductor light receiving element comprises: a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a non-doped semiconductor light absorbing layer formed on the semiconductor layer of the first conductivity type, a semiconductor layer of a second conductivity type formed on the non-doped semiconductor light absorbing layer, and an electro-conductive layer formed on the semiconductor layer of the second conductivity type. A plurality of openings, periodically arrayed, are formed in a laminated body composed of the electro-conductive layer, the semiconductor layer of the second conductivity type, and the non-doped semiconductor light absorbing layer. The widths of the openings are less than or equal to the wavelength of incident light, and the openings pass through the electro-conductive layer and the semiconductor layer of the second conductivity type to reach the non-doped semiconductor light absorbing layer.
    Type: Application
    Filed: January 9, 2009
    Publication date: December 9, 2010
    Inventors: Daisuke Okamoto, Junichi Fujikata, Kenichi Nishi
  • Patent number: 7800193
    Abstract: Both high light receiving sensitivity and high speed of a photodiode are achieved at the same time. The photodiode is provided with a semiconductor layer (1) and a pair of metal electrodes (2) which are arranged on the surface of the semiconductor layer (1) at an interval (d) and form an MSM junction. The interval (d) satisfies the relationship of ?>d>?/100, where ? is the wavelength of incident light. The metal electrodes (2) can induce surface plasmon. At least one of the electrodes forms a Schottky junction with the semiconductor layer (1), and a low end portion is embedded in the semiconductor layer (1) to a position at a depth less than ?/2n, where n is the refractive index of the semiconductor layer (1).
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: September 21, 2010
    Assignee: NEC Corporation
    Inventors: Junichi Fujikata, Keishi Ohashi
  • Publication number: 20100200941
    Abstract: Intended is to provide a device structure, which makes the light receiving sensitivity and the high speediness of a photodiode compatible. Also provided is a Schottky barrier type photodiode having a conductive layer formed on the surface of a semiconductor layer. The photodiode is so constituted that a light can be incident on the back side of the semiconductor layer, and that a periodic structure, in which a light incident from the back side of the semiconductor layer causes a surface plasmon resonance, is made around the Schottky junction of the photodiode.
    Type: Application
    Filed: November 28, 2007
    Publication date: August 12, 2010
    Inventors: Junichi Fujikata, Daisuke Okamoto, Kikuo Makita, Kenichi Nishi, Keishi Ohashi
  • Patent number: 7728366
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: June 1, 2010
    Assignee: NEC Corporation
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Publication number: 20100119192
    Abstract: In a waveguide path coupling-type photodiode, a semiconductor light absorbing layer and an optical waveguide path core are adjacently arranged. An electrode formed of at least one layer is installed in a boundary part of the semiconductor light absorbing layer and the optical waveguide path core. The electrodes are arranged at an interval of (1/100)? to ? [?: wavelength of light transmitted through optical waveguide path core]. At least a part of the electrodes is embedded in the semiconductor light absorbing layer. Embedding depth from a surface of the semiconductor light absorbing layer is a value not more than ?/(2ns) [ns: refractive index of semiconductor light absorbing layer]. At least one layer of the electrode is constituted of a material which can surface plasmon-induced.
    Type: Application
    Filed: April 30, 2008
    Publication date: May 13, 2010
    Applicants: NEC CORPORATION, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Junichi Fujikata, Jun Ushida, Daisuke Okamoto, Kenichi Nishi, Keishi Ohashi, Tai Tsuchizawa, Seiichi Itabashi
  • Publication number: 20100013040
    Abstract: A photodiode includes: an upper spacer layer including a semiconductor transparent to incident light; a metal periodic structure provided on the upper spacer layer and arranged to induce surface plasmon, the metal periodic structure including first and second electrodes including portions arranged alternately on the upper spacer layer; a light absorption layer formed under the upper spacer layer and including a semiconductor having a refractive index higher than that of the upper spacer layer; and a lower spacer layer formed under the light absorption layer and having a refractive index smaller than that of the light absorption layer. Each of the first and second electrodes forms a Schottky barrier junction with the upper spacer layer.
    Type: Application
    Filed: December 13, 2007
    Publication date: January 21, 2010
    Applicant: NEC CORPORATION
    Inventors: Daisuke Okamoto, Junichi FuJikata, Kenichi Nishi, Keishi Ohashi
  • Publication number: 20090176327
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Application
    Filed: March 11, 2009
    Publication date: July 9, 2009
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Publication number: 20090134486
    Abstract: Both high light receiving sensitivity and high speed of a photodiode are achieved at the same time. The photodiode is provided with a semiconductor layer (1) and a pair of metal electrodes (2) which are arranged on the surface of the semiconductor layer (1) at an interval (d) and form an MSM junction. The interval (d) satisfies the relationship of ?>d>?100, where ? is the wavelength of incident light. The metal electrodes (2) can induce surface plasmon. At least one of the electrodes forms a Schottky junction with the semiconductor layer (1), and a low end portion is embedded in the semiconductor layer (1) to a position at a depth less than ?/2n, where n is the refractive index of the semiconductor layer (1).
    Type: Application
    Filed: March 8, 2007
    Publication date: May 28, 2009
    Applicant: NEC CORPORATION
    Inventor: Junichi Fujikata
  • Patent number: 7369375
    Abstract: A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A first magnetic layer is provided on the lower conductive layer. On the first magnetic layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 6, 2008
    Assignee: NEC Corporation
    Inventors: Kazuhiko Hayashi, Junichi Fujikata, Tsutomu Ishi, Shigeru Mori, Keishi Ohashi, Masafumi Nakada, Kiyokazu Nagahara, Kunihiko Ishihara, Nobuyuki Ishiwata
  • Patent number: 7298596
    Abstract: A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 20, 2007
    Assignee: NEC Corporation
    Inventors: Kazuhiko Hayashi, Junichi Fujikata, Tsutomu Ishi, Shigeru Mori, Keishi Ohashi, Masafumi Nakada, Kiyokazu Nagahara, Kunihiko Ishihara, Nobuyuki Ishiwata
  • Patent number: 7277261
    Abstract: A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. Furthermore, an upper conductive layer is provided on the upper layer and an insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 2, 2007
    Assignee: NEC Corporation
    Inventors: Kazuhiko Hayashi, Junichi Fujikata, Tsutomu Ishi, Shigeru Mori, Keishi Ohashi, Masafumi Nakada, Kivokazu Nagahara, Kunihiko Ishihara, Nobuyuki Ishiwata
  • Patent number: 7265949
    Abstract: A magneto-resistance effect element is adapted that a non-magnetic layer (9, 18), a free layer (3b, 19), another non-magnetic layer (4, 25), a fixed layer (5, 26), and a fixing layer (6b, 27) are formed vertically symmetric with respect to a first magnetic layer (8b), to which a vertical bias magnetic field is applied from an underlying layer (2a) for a vertical bias layer (2b). The magneto-resistance effect element operates in CPP mode. Generally, the free layer is unavoidably subjected to the influence of a circular electric magnetic field caused by a current flowing perpendicularly to the film surface. However, in the magneto-resistance effect element, the influence of the electric magnetic field to which the free layer (3b) is subjected is opposite to that of the electric magnetic field to which the second free layer (19) is subjected, thereby canceling out the influences as a hole.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 4, 2007
    Assignee: NEC Corporation
    Inventors: Kazuhiko Hayashi, Junichi Fujikata, Tsutomu Ishi, Shigeru Mori, Keishi Ohashi, Masafumi Nakada, Kiyokazu Nagahara, Kunihiko Ishihara, Nobuyuki Ishiwata
  • Publication number: 20070194357
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Application
    Filed: April 5, 2005
    Publication date: August 23, 2007
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Publication number: 20070047158
    Abstract: A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.
    Type: Application
    Filed: June 30, 2006
    Publication date: March 1, 2007
    Inventors: Kazuhiko Hayashi, Junichi Fujikata, Tsutomu Ishi, Shigeru Mori, Keishi Ohashi, Masafumi Nakada, Kiyokazu Nagahara, Kunihiko Ishihara, Nobuyuki Ishiwata
  • Patent number: 7161774
    Abstract: A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: January 9, 2007
    Assignee: NEC Corporation
    Inventors: Kazuhiko Hayashi, Junichi Fujikata, Tsutomu Ishi, Shigeru Mori, Keishi Ohashi, Masafumi Nakada, Kiyokazu Nagahara, Kunihiko Ishihara, Nobuyuki Ishiwata