Abstract: A semiconductor device is provided. The semiconductor can apply different voltages to sources and bases (bulks, N-type well) of pull-up transistors and improves write margin of memory cells. An SRAM of the invention includes P-well regions PW_1 and PW_2, an N-well region NW, a first metal wire M1, and a second metal wire M2. The P-well regions PW_1 and PW_2 extend in a first direction, and pull-down transistors and accessing transistors are formed therein. The N-well region NW extends in first direction, and pull-up transistors are formed therein. The first metal wire M1 extends in the first direction on the N-well region NW and is electrically connected to the N-well region NW. The second metal wire M2 extends in a second direction orthogonal to the first direction and electrically connected to a common S/D region of a pair of pull-up transistors that are formed in the N-well region NW.

Abstract: A test device capable of measuring characteristics of respective transistors constituting a memory cell is provided. The test device for testing a SRAM connects a resistor to a bit line on one side of a memory cell selected by a word line selection circuit and a bit line selection circuit of the SRAM. In a manner that a selected transistor and a resistor of the memory cell constitute a source follower circuit, the test device applies a voltage to each portion of the memory cell, applies an input voltage to a gate of the transistor constituting the source follower circuit, and inputs an output voltage outputted from a source of the transistor constituting the source follower circuit.

Abstract: A semiconductor device is provided. The semiconductor can apply different voltages to sources and bases (bulks, N-type well) of pull-up transistors and improves write margin of memory cells. An SRAM of the invention includes P-well regions PW_1 and PW_2, an N-well region NW, a first metal wire M1, and a second metal wire M2. The P-well regions PW_1 and PW_2 extend in a first direction, and pull-down transistors and accessing transistors are formed therein. The N-well region NW extends in first direction, and pull-up transistors are formed therein. The first metal wire M1 extends in the first direction on the N-well region NW and is electrically connected to the N-well region NW. The second metal wire M2 extends in a second direction orthogonal to the first direction and electrically connected to a common S/D region of a pair of pull-up transistors that are formed in the N-well region NW.

Abstract: A test device capable of measuring characteristics of respective transistors constituting a memory cell is provided. The test device for testing a SRAM connects a resistor to a bit line on one side of a memory cell selected by a word line selection circuit and a bit line selection circuit of the SRAM. In a manner that a selected transistor and a resistor of the memory cell constitute a source follower circuit, the test device applies a voltage to each portion of the memory cell, applies an input voltage to a gate of the transistor constituting the source follower circuit, and inputs an output voltage outputted from a source of the transistor constituting the source follower circuit.

Abstract: A signal charge corresponding to an incident light quantity is accumulated in a first node of each pixel circuit. An accumulated charge exhaust circuit includes each of first nodes of the plurality of pixel circuits belonging to the same pixel group, and a second node connected through discharge gates functioning as variable resistance elements. Second node functions as a floating drain during an ON period of a control switch, while accumulating the signal charge overflowing from each pixel circuit, in a capacitor during an OFF period of control switch provided at an intermediate timing in one frame period. When the incident light to the pixel group is intense, a resistance value of each discharge gate is lowered in response to an increase of the signal charge accumulated in capacitor, so that the signal charge accumulated in each pixel circuit can be exhausted once at the above intermediate timing.

Abstract: A semiconductor image pickup device's pixel circuits each include a photodetection element, and first and second current mirror circuits provided as current generation circuit. The photodetection element generates at a node a photocurrent corresponding to a quantity of light received. The first current mirror circuit passes first and second currents corresponding to the photocurrent to an internal node and an output node, respectively. The second current mirror circuit is connected to generate a fourth current corresponding to a third current passing through the internal node and also allow a differential current between the second and fourth currents to flow through the output node. Each pixel circuit has its internal node electrically connected by a resistance component, which implements an inter-pixel connect, to the internal node of at least one of adjacent pixel circuits.

Abstract: A semiconductor pickup device includes a pixel circuit including: a photodiode passing to a prescribed node a current of a value corresponding to intensity of light received; a log transistor operating in a log region when the prescribed node is increased in potential; and a reset transistor operative for the prescribed node's potential higher than a threshold potential to reset in response to a reset signal the prescribed node's potential to a reset potential, and operative for the prescribed node's potential lower than the threshold potential to avoid the resetting. For low illuminance the pixel circuit decreases in frame rate and lower minimum illuminance required for pickup can be provided.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: A semiconductor pickup device includes a pixel circuit including: a photodiode passing to a prescribed node a current of a value corresponding to intensity of light received; a log transistor operating in a log region when the prescribed node is increased in potential; and a reset transistor operative for the prescribed node's potential higher than a threshold potential to reset in response to a reset signal the prescribed node's potential to a reset potential, and operative for the prescribed node's potential lower than the threshold potential to avoid the resetting. For low illuminance the pixel circuit decreases in frame rate and lower minimum illuminance required for pickup can be provided.

Abstract: A semiconductor image pickup device's pixel circuits each include a photodetection element, and first and second current mirror circuits provided as current generation circuit. The photodetection element generates at a node a photocurrent corresponding to a quantity of light received. The first current mirror circuit passes first and second currents corresponding to the photocurrent to an internal node and an output node, respectively. The second current mirror circuit is connected to generate a fourth current corresponding to a third current passing through the internal node and also allow a differential current between the second and fourth currents to flow through the output node. Each pixel circuit has its internal node electrically connected by a resistance component, which implements an inter-pixel connect, to the internal node of at least one of adjacent pixel circuits.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient &bgr; of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.