Abstract: An integrated circuit device for processing an image signal has an inexpensive structure and an excellent signal processing characteristic. The integrated circuit device (3) formed on one integrated circuit substrate comprises a switch circuit (4), a separator circuit (8) and preamp circuits (5) to (7). The separator circuit (8) has an input terminal which has an input impedance which is sufficiently higher than an output impedance of the switch circuit (4). Receiving an output of the switch circuit (4) at such an input terminal, the separator circuit (8) filters off high-frequency components including the maximum frequency of the image signal and outputs signal components which belong to a frequency band which is related to a synchronization signal. The preamp circuits (5) to (7) amplify and output image signals which are outputted by the switch circuit (4).

Abstract: An internal control voltage outputted from a voltage comparator controls the gain of a second amplifier. The output from the second amplifier, supplied to one input of the voltage comparator, is compared with an external control voltage supplied to the other input thereof. Such a negative feedback loop enables the gain of the second amplifier to be completely proportional to the external control voltage over the full variable gain range. The internal control voltage outputted from the voltage comparator is also inputted to a first amplifier, which includes a first variable gain portion having the same variable gain characteristic as a second variable gain portion of the second amplifier. Therefore, the gain of the first amplifier is completely proportional to the external control voltage over the full variable gain range as well as the gain of the second amplifier.

Abstract: A video intermediate frequency signal processing circuit according to the present invention is so structured that a PLL state and a holding state are switched in response to a locking detection signal, a signal strength detection signal and a modulation factor detection signal. Thus, when it is set to enter the holding state at timing when the modulation factor of the video intermediate frequency signal is deep on the basis of the modulation factor detection signal, PLL output will not follow a video intermediate frequency signal at timing when the modulation factor is deep but follows only a video intermediate frequency signal at timing when the modulation factor is shallow, whereby correct video detection output can be regularly derived.

Abstract: A video intermediate frequency signal processing circuit includes synchronous detection circuit (77) which receives a video intermediate frequency signal through a path including a bandpass filter (51), a phase locked loop circuit (59) and an automatic phase control loop (67), and another path including another bandpass filter (53). Both signals received by the synchronous detection circuit (77) are maintained to be the same in phase by virtue of the operation of the automatic phase control loop (67), so that the synchronous detection circuit (77) generates a video detection output signal including a video signal accurately demodulated and a sound intermediate frequency signal having no phase modulation component causing a sound buzz.

Abstract: The gain of a video intermediate frequency signal processing circuit (11) is varied in accordance with the charge voltage of a capacitor (C.sub.1). The capacitor (C.sub.1) is charged with a relatively small current when the peak of a video detection signal does not reach a reference voltage (V.sub.A) and discharged with a relatively large current when reaches. A current source (29) for rapid charge is activated when the peak of the video detection signal does not reach the reference voltage (V.sub.A) over a predetermined period longer than one horizontal synchronous period, to rapidly charge the capacitor (C.sub.1). Thus, a speed in increase of the gain of the video intermediate frequency signal processing circuit is quickened, to hasten the restoration of an amplitude of the video detection signal.

Abstract: An input synchronizing signal is subjected to mean DC voltage adjustment so that the mean DC voltage thereof becomes a prescribed level. The input synchronizing signal after the mean DC voltage adjustment is compared with first reference voltage which is higher than the prescribed level and second reference voltage which is lower than the prescribed level by comparators, to derive an output synchronizing signal of constant polarity and amplitude or a polarity detection output for the input synchronizing signal.