Patents by Inventor Junichi Iimura
Junichi Iimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8338234Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.Type: GrantFiled: July 30, 2008Date of Patent: December 25, 2012Assignee: Semiconductor Components Industries, LLCInventors: Junichi Iimura, Yasuhiro Koike, Soichi Izutani
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Patent number: 7609498Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select oneType: GrantFiled: September 19, 2006Date of Patent: October 27, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
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Publication number: 20090011548Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.Type: ApplicationFiled: July 30, 2008Publication date: January 8, 2009Applicant: SANYO ELECTRIC CO., LTDInventors: Junichi Iimura, Yasuhiro Koike, Soichi Izutani
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Publication number: 20070014065Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select oneType: ApplicationFiled: September 19, 2006Publication date: January 18, 2007Applicant: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
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Patent number: 7136269Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select oneType: GrantFiled: April 24, 2003Date of Patent: November 14, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
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Patent number: 7075762Abstract: In order to enable overheat protection and overcurrent protection as well as temperature detection of an inverter circuit, an inverter circuit comprises a switching circuit 9 composed of a plurality of switching elements and a control circuit 1 for generating a control signal to be inputted into a drive circuit 2 to control a load, a temperature detecting element 12 for detecting a change in temperature of the inverter circuit is provided in a temperature detection circuit 10, and a temperature detection signal which changes according to a change in temperature of said inverter circuit, an overheat abnormal signal outputted upon a rise in temperature to a predetermined temperature or more, and an overcurrent abnormal signal outputted from an overcurrent protection FET 13 are outputted via one commonly used terminal.Type: GrantFiled: June 30, 2003Date of Patent: July 11, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
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Publication number: 20060033209Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.Type: ApplicationFiled: October 11, 2005Publication date: February 16, 2006Applicant: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
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Patent number: 6974727Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.Type: GrantFiled: June 27, 2002Date of Patent: December 13, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
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Patent number: 6975024Abstract: In a manufacturing method of a hybrid integrated circuit device of the invention, transfer molding is carried put by positioning a curved surface formed in a back surface of the substrate on a lower mold die side and a burr formed in a main surface of the substrate on an upper mold die side. This utilizes the curved surface to inject thermosetting resin in an arrow direction to pour the thermosetting resin through a below of the substrate. There are no broken fragments of burr in a thermosetting resin at the below of the substrate. As a result, a required minimum resin thickness is secured at the below of the substrate, thus realizing a hybrid integrated circuit device having a high voltage resistance, an excellent heat dissipation property and a high product quality.Type: GrantFiled: June 27, 2002Date of Patent: December 13, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuhiro Koike, Hidefumi Saito, Katsumi Okawa, Junichi Iimura
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Publication number: 20050212113Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.Type: ApplicationFiled: March 29, 2005Publication date: September 29, 2005Applicant: SANYO ELECTRIC CO., LTD.Inventors: Junichi Iimura, Yasuhiro Koike, Soichi Izutani
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Publication number: 20040008457Abstract: In order to enable overheat protection and overcurrent protection as well as temperature detection of an inverter circuit, an inverter circuit comprises a switching circuit 9 composed of a plurality of switching elements and a control circuit 1 for generating a control signal to be inputted into a drive circuit 2 to control a load, a temperature detecting element 12 for detecting a change in temperature of the inverter circuit is provided in a temperature detection circuit 10, and a temperature detection signal which changes according to a change in temperature of said inverter circuit, an overheat abnormal signal outputted upon a rise in temperature to a predetermined temperature or more, and an overcurrent abnormal signal outputted from an overcurrent protection FET 13 are outputted via one commonly used terminal.Type: ApplicationFiled: June 30, 2003Publication date: January 15, 2004Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
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Publication number: 20030227730Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select oneType: ApplicationFiled: April 24, 2003Publication date: December 11, 2003Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
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Patent number: 6593169Abstract: In a molding process, a hybrid integrated circuit substrate is positionally fixed in a horizontal direction. By abutting the points, where particularly leads having a spacing kept constant continue with a first connection portion, against guide pins provided on a mold die, a hybrid integrated circuit substrate can be positionally fixed. Because the spacing between the particular leads is not relied upon the number of terminals of the hybrid integrated circuit substrate, the mold can be commonly used where the number of terminals is different.Type: GrantFiled: June 27, 2002Date of Patent: July 15, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
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Publication number: 20030001255Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.Type: ApplicationFiled: June 27, 2002Publication date: January 2, 2003Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
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Publication number: 20030003630Abstract: In a molding process, a hybrid integrated circuit substrate is positionally fixed in a horizontal direction. By abutting the points, where particularly leads having a spacing kept constant continue with a first connection portion, against guide pins provided on a mold die, a hybrid integrated circuit substrate can be positionally fixed. Because the spacing between the particular leads is not relied upon the number of terminals of the hybrid integrated circuit substrate, the mold can be commonly used where the number of terminals is different.Type: ApplicationFiled: June 27, 2002Publication date: January 2, 2003Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
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Publication number: 20030003629Abstract: In a manufacturing method of a hybrid integrated circuit device of the invention, transfer molding is carried put by positioning a curved surface formed in a back surface of the substrate on a lower mold die side and a burr formed in a main surface of the substrate on an upper mold die side. This utilizes the curved surface to inject thermosetting resin in an arrow direction to pour the thermosetting resin through a below of the substrate. There are no broken fragments of burr in a thermosetting resin at the below of the substrate. As a result, a required minimum resin thickness is secured at the below of the substrate, thus realizing a hybrid integrated circuit device having a high voltage resistance, an excellent heat dissipation property and a high product quality.Type: ApplicationFiled: June 27, 2002Publication date: January 2, 2003Inventors: Yasuhiro Koike, Hidefumi Saito, Katsumi Okawa, Junichi Iimura
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Patent number: 6037099Abstract: Opposed faces of two disk substrates are bonded by an adhesive layer whose characteristic parameters are set in predetermined ranges, particularly in the values of a product of Young's modulus and the film thickness in a range of 1.0.times.10.sup.-2 kg/mm to 3.0 kg/mm, a product of Young's module and the thermal expansion coefficient in a range not larger than 1.5.times.10.sup.-2 kg.multidot.mm.sup.-2 .multidot..degree. C..sup.-1, or a product of the thermal expansion coefficient and the film thickness in a range not larger than 2.0.times.10.sup.-5 mm /.degree. C. Preferably, the glass transition point of the used adhesive is set to a value in a range of 20.degree. C. to 80.degree. C., and the film thickness is set to a value in a range of 10 .mu.m to 100 .mu.m.Type: GrantFiled: May 30, 1997Date of Patent: March 14, 2000Assignee: Victor Company of Japan Ltd.Inventors: Takashi Oogo, Junichi Iimura