Patents by Inventor Junichi Inagaki

Junichi Inagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7756144
    Abstract: A parallel computer operates to reduce data held by a plurality of nodes. Each node constituting a parallel computer transfers the data divided into n to other nodes, and each node summarizes the respective 1/n data and operates, then a plurality of nodes transfer the respective operation result to a summarizing node. Since all the nodes execute operation for divided data respectively, reduction processing time can be decreased. And more nodes (network adapters) can participate in data transfer through the first and second data transfers, high-speed transfer processing can therefore be implemented, and transfer time can be decreased.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Limited
    Inventors: Junichi Inagaki, Masao Koyabu
  • Publication number: 20100096591
    Abstract: The purpose the invention is to provide a polymerizable liquid crystal compound which has an excellent solubility with other compounds, a high homeotropic property, and a spirobiindan-backbone, and a liquid crystal composition comprising this compound. The purpose is attained with a polymerizable liquid crystal compound represented by Formula (1). A polymer which is excellent in many characteristics can be obtained from this compound and a formed body having optical anisotropy, produced from this polymer can be obtained. In Formula (1), G is a single bond or oxygen; R is hydrogen, methyl (Me) or a group represented by Formula (a), wherein at least two of R are groups represented by Formula (a); P is a polymerizable group represented by any of Formula (P1) to Formula (P8). In Formula (a), a desirable A is 1,4-cyclohexylene or 1,4-phenylene; Z is a bonding group; m is an integer of 0 to 3; X0 is a single bond or alkylene; Z0 is a single bond, —O—, —OCO—, or —OCOO—; X is a single bond or alkylene.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 22, 2010
    Inventors: Maiko ITOH, Yoshiharu HIRAI, Junichi INAGAKI, Daisuke OOTSUKI
  • Patent number: 7602868
    Abstract: The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: October 13, 2009
    Assignee: Fujitsu Limited
    Inventors: Jun Tsuiki, Masao Koyabu, Masahiro Kuramoto, Junichi Inagaki
  • Publication number: 20090231517
    Abstract: There is provided a liquid crystal display apparatus having a high contrast ratio in an oblique direction and small color change depending upon a viewing angle. A liquid crystal panel according to an embodiment of the present invention includes: a liquid crystal cell; a first polarizer placed on one side of the liquid crystal cell; a second polarizer placed on the other side of the liquid crystal cell; a first O-plate placed between the liquid crystal cell and the first polarizer; a second O-plate placed between the liquid crystal cell and the second polarizer; a first biaxial retardation layer placed between the liquid crystal cell and the first O-plate; and a second biaxial retardation layer placed between the liquid crystal cell and the second O-plate.
    Type: Application
    Filed: April 5, 2007
    Publication date: September 17, 2009
    Applicant: NITTO DENKO CORPORATION
    Inventors: Miki Shiraogawa, Junichi Inagaki
  • Patent number: 7555699
    Abstract: A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: June 30, 2009
    Assignee: Fujitsu Limited
    Inventors: Masahiro Kuramoto, Masao Koyabu, Jun Tsuiki, Junichi Inagaki
  • Patent number: 7475170
    Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: January 6, 2009
    Assignee: Fujitsu Limited
    Inventors: Junichi Inagaki, Masao Koyabu, Jun Tsuiki, Masahiro Kuramoto
  • Publication number: 20070226288
    Abstract: A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism computes the sums only for a group of which exponent sections have a highest value and a group of which exponent sections have a second highest value, and adds the sum of the group of which the exponent sections have a highest value and the sum of the group of which the exponent sections have a second highest value. By this, the consistency of the computation result can be guaranteed even if the sum is computed regardless the computing sequence of the values.
    Type: Application
    Filed: June 27, 2006
    Publication date: September 27, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Inagaki, Masao Koyabu, Hiroaki Ishihata
  • Publication number: 20070217450
    Abstract: A network system broadcast data from one node to a plurality of other nodes, which can decrease the time required for broadcast. A transfer source node divides the transfer data to be broadcasted, and transfers each divided data separately from the network adapters of the transfer source node to the network adapters of the other nodes, and the other nodes transfer the received data to the network adapters of the other nodes other than the transfer source node. Since more nodes (network adapters) can participate in data transfer in the second data transfer, high-speed transfer processing can be implemented, and the transfer processing time for broadcast can be decreased.
    Type: Application
    Filed: June 23, 2006
    Publication date: September 20, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Inagaki, Masao Koyabu
  • Publication number: 20070220164
    Abstract: A parallel computer operates to reduce data held by a plurality of nodes. Each node constituting a parallel computer transfers the data divided into n to other nodes, and each node summarizes the respective 1/n data and operates, then a plurality of nodes transfer the respective operation result to a summarizing node. Since all the nodes execute operation for divided data respectively, reduction processing time can be decreased. And more nodes (network adapters) can participate in data transfer through the first and second data transfers, high-speed transfer processing can therefore be implemented, and transfer time can be decreased.
    Type: Application
    Filed: June 23, 2006
    Publication date: September 20, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Inagaki, Masao Koyabu
  • Publication number: 20070116165
    Abstract: The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead.
    Type: Application
    Filed: January 30, 2006
    Publication date: May 24, 2007
    Inventors: Jun Tsuiki, Masao Koyabu, Masahiro Kuramoto, Junichi Inagaki
  • Publication number: 20060236205
    Abstract: A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.
    Type: Application
    Filed: September 28, 2005
    Publication date: October 19, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Kuramoto, Masao Koyabu, Jun Tsuiki, Junichi Inagaki
  • Publication number: 20060212661
    Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.
    Type: Application
    Filed: July 25, 2005
    Publication date: September 21, 2006
    Applicant: Fujitsu Limited
    Inventors: Junichi Inagaki, Masao Koyabu, Jun Tsuiki, Masahiro Kuramoto
  • Patent number: 6861160
    Abstract: The zinc-base plated steel sheet has a steel sheet, a zinc-base plating layer on the steel sheet, and a composite coating film formed on the plating layer, which composite coating layer contains a P ingredient, an N ingredient, and at least one element selected from the group consisting of Mg, Al, Ca, Ti, Fe, Co, Ni, Cu, and Mo, and is prepared by applying an aqueous solution containing a cationic ingredient (?) and a phosphoric acid ingredient (?) onto the surface of plating layer on the zinc-base plated steel sheet, and then drying the applied aqueous solution, without giving washing with water, and which cationic ingredient (?) consists essentially of at least one metallic ion selected from the group consisting of Mg, Al, Ca, Ti, Fe, Co, Ni, Cu, Mo, and NH4+ ions.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: March 1, 2005
    Assignee: JFE Steel Corporation
    Inventors: Satoru Ando, Masaki Tada, Yoshiharu Sugimoto, Masaaki Yamashita, Tomoko Inagaki, Junichi Inagaki
  • Patent number: 6797411
    Abstract: The method for manufacturing galvanized steel sheet has a step of adjusting the surface texture thereof by blasting solid particles against the surface thereof. The surface texture is defined by at least one parameter selected from the group of parameters consisting of mean roughness Ra on the surface of steel sheet, peak count PPI on the surface of steel sheet, and filtered centerline waviness Wca on the surface of steel sheet. The galvanized steel sheet has a surface in dimple-pattern texture.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: September 28, 2004
    Assignee: NKK Corporation
    Inventors: Yasuhiro Sodani, Yukio Kimura, Masayasu Ueno, Shogo Tomita, Hisato Noro, Kaoru Sato, Yoshiharu Sugimoto, Satoru Ando, Masaki Tada, Junichi Inagaki, Masaaki Yamashita, Yuji Yamasaki
  • Patent number: 6699592
    Abstract: The invention provides a galvannealed steel sheet which has an oxide layer having 10 nm or larger thickness on the plateau of the coating layer flattened by temper rolling. With the use of the galvannealed steel sheet, no powdering occurs during press-forming, and stable and excellent sliding performance is attained. By selecting the area percentage of the plateau of the flattened coating layer to a range from 20 to 80%, making the coating layer single layer of &dgr;1 phase, and letting &zgr; phase exist in the &dgr;1 phase, further improved sliding performance and anti-powdering property are obtained.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: March 2, 2004
    Assignee: NKK Corporation
    Inventors: Shoichiro Taira, Yoshiharu Sugimoto, Junichi Inagaki, Toru Imokawa, Shuji Nomura, Michitaka Sakurai, Masaaki Yamashita, Kaoru Sato, Masayasu Nagoshi, Akira Gamou, Yoichi Miyakawa, Shunsaku Node, Masahiro Iwabuchi
  • Publication number: 20030219621
    Abstract: The method for manufacturing galvanized steel sheet has a step of adjusting the surface texture thereof by blasting solid particles against the surface thereof. The surface texture is defined by at least one parameter selected from the group of parameters consisting of mean roughness Ra on the surface of steel sheet, peak count PPI on the surface of steel sheet, and filtered centerline waviness Wca on the surface of steel sheet. The galvanized steel sheet has a surface in dimple-pattern texture.
    Type: Application
    Filed: June 18, 2003
    Publication date: November 27, 2003
    Applicant: NKK CORPORATION
    Inventors: Yasuhiro Sodani, Yukio Kimura, Masayasu Ueno, Shogo Tomita, Hisato Noro, Kaoru Sato, Yoshiharu Sugimoto, Satoru Ando, Masaki Tada, Junichi Inagaki, Masaaki Yamashita, Yuji Yamasaki
  • Publication number: 20030175548
    Abstract: The invention provides a galvannealed steel sheet which has an oxide layer having 10 nm or larger thickness on the plateau of the coating layer flattened by temper rolling. With the use of the galvannealed steel sheet, no powdering occurs during press-forming, and stable and excellent sliding performance is attained. By selecting the area percentage of the plateau of the flattened coating layer to a range from 20 to 80%, making the coating layer single layer of &dgr;1 phase, and letting &zgr; phase exist in the &dgr;1 phase, further improved sliding performance and anti-powdering property are obtained.
    Type: Application
    Filed: October 21, 2002
    Publication date: September 18, 2003
    Inventors: Shoichiro Taira, Yoshiharu Sugimoto, Junichi Inagaki, Tomoko Inagaki, Toru Imokawa, Shuji Nomura, Michitaka Sakurai, Masaaki Yamashita, Kaoru Sato, Masayasu Nagoshi, Akira Gamou, Yoichi Miyakawa, Shunsaku Node, Masahiro Iwabuchi
  • Patent number: 6610422
    Abstract: The method for manufacturing coated steel sheet has the steps of: immersing a steel sheet in a hot-dip coating bath to form an Al—Zn base coating layer containing 20 to 95 mass % Al on the steel sheet, forming a passivated layer on the coating layer; and applying thermal history to the coating layer. The thermal history is applied immediately after the steel sheet left the hot-dip coating bath or in a temperature range of from T(° C.) between 130° C. and 300° C. to 100° C.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 26, 2003
    Assignee: NKK Corporation
    Inventors: Toshihiko Ooi, Takafumi Yamaji, Keiji Yoshida, Yuichiro Tanaka, Junichi Inagaki, Masaaki Yamashita, Yasuhiro Majima, Nobuyuki Ishida, Yuichi Fukushima, Norio Inoue, Shinji Hori
  • Publication number: 20030012978
    Abstract: The method for manufacturing galvanized steel sheet has a step of adjusting the surface texture thereof by blasting solid particles against the surface thereof. The surface texture is defined by at least one parameter selected from the group of parameters consisting of mean roughness Ra on the surface of steel sheet, peak count PPI on the surface of steel sheet, and filtered centerline waviness Wca on the surface of steel sheet. The galvanized steel sheet has a surface in dimple-pattern texture.
    Type: Application
    Filed: June 17, 2002
    Publication date: January 16, 2003
    Applicant: NKK CORPORATION
    Inventors: Yasuhiro Sodani, Yukio Kimura, Masayasu Ueno, Shogo Tomita, Hisato Noro, Kaoru Sato, Yoshiharu Sugimoto, Satoru Ando, Masaki Tada, Junichi Inagaki, Masaaki Yamashita, Yuji Yamasaki
  • Patent number: 6129995
    Abstract: A zinciferous coated steel sheet comprises a steel sheet, a zinciferous coating layer formed on the steel sheet, a Fe--Ni--Zn--O film formed on the zinciferous coating layer, and an oxide layer formed on a surface portion of the Fe--Ni--Zn--O film. The method comprises providing an electrolyte of an acidic sulfate aqueous solution, carrying out an electrolysis treatment in the electrolyte under a current density ranging from 1 to 150 A/dm.sup.2, and carrying out an oxidation treatment to a surface of the zinciferous coated steel sheet.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: October 10, 2000
    Assignee: NKK Corporation
    Inventors: Satoshi Hashimoto, Toru Imokawa, Michitaka Sakurai, Takayuki Urakawa, Junichi Inagaki, Masaru Sagiyama