Patents by Inventor Junichi Inazumi

Junichi Inazumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Row/column address interchange for a fault-tolerant memory system
    Patent number: 5109360
    Abstract: A memory system in which access to faulty memory blocks is prevented. A test is carried out to see if there are enough functional memory blocks to store a given amount of information. If not, an address mode signal is generated that interchanges the row/column accesses for a given multi-bit address word, such that a line fault is isolated to only one memory block. This reconfigures the system to maximize available memory space without adding excessive access delays.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: April 28, 1992
    Assignee: International Business Machines Corporation
    Inventors: Junichi Inazumi, Shigetaka Inazumi, Jun Nakamoto