Abstract: A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

Abstract: A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

Abstract: A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

Abstract: For realizing a memory access control circuit giving a high degree of protection against a fraudulent access, an instruction fetch address register 14 holds the value of a program counter 11, a first area table 15 holds an address of a region to be protected in a memory, and a second area table 16 holds an address of an instruction allowed to access to the region to be protected. An access detecting circuit 17 compares an address of an access destination obtained as the result of an instruction decoding, with the address of the first area table 15, in order to discriminated whether or not the instruction is an instruction accessing to the region to be protected.

Abstract: Display data is read out from a display memory in parallel, and is temporarily held in a first shift register located near to the display memory. The display data is serially read out and transferred from the first shift register in one bit unit to a second shift register located near to an display data latch, in synchronism with a shift clock signal outputted from a shift clock controlling circuit. The display data held in the second shift register is outputted in parallel to the display data latch in accordance with a display data read signal. Thus, it is possible to reduce the increase of the number of the wiring lines extending from the display memory to the display data latch, as well as the increase of the chip area, both of which would be caused by the increase of the display segments. It is also possible to reduce the limitations related to the arrangement of the interior of the microcomputer.