Patents by Inventor Junichi Kogure

Junichi Kogure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8921927
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Yuya Abiko, Junichi Kogure
  • Publication number: 20140284705
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Application
    Filed: June 10, 2014
    Publication date: September 25, 2014
    Inventors: Satoshi EGUCHI, Yuya ABIKO, Junichi KOGURE
  • Patent number: 8796094
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Yuya Abiko, Junichi Kogure
  • Publication number: 20140120669
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 1, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi EGUCHI, Yuya ABIKO, Junichi KOGURE
  • Patent number: 8647948
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: February 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Yuya Abiko, Junichi Kogure