Abstract: An orthodontic implant structure (2) that is used by being implanted in bone in an oral cavity includes a first screw (6, 6B) having a screw body (6b) and an engaging portion (14), a plate securing implement (12, 13), a second screw, and a base plate having a first surface (4p) and a second surface (4q) and in which a first attachment hole (24A, 24B) and a second attachment hole (26) are formed.

Abstract: An orthodontic implant structure (2) that is used by being implanted in bone in an oral cavity includes a first screw (6, 6B) having a screw body (6b) and an engaging portion (14), a plate securing implement (12, 13), a second screw, and a base plate having a first surface (4p) and a second surface (4q) and in which a first attachment hole (24A, 24B) and a second attachment hole (26) are formed.

Abstract: An orthodontic connection tool for attaching to a screw that has been embedded in a bone in the oral cavity an upper structural body to which an orthodontic tool is fixed, the orthodontic connection tool being provided with a base plate that is engageable with the screw; and a structural body fixture that is engaged with the base plate at an arbitrary position thereof and that fixes the upper structural body in a detachable manner.

Abstract: An orthodontic connection tool for attaching to a screw that has been embedded in a bone in the oral cavity an upper structural body to which an orthodontic tool is fixed, the orthodontic connection tool being provided with a base plate that is engageable with the screw; and a structural body fixture that is engaged with the base plate at an arbitrary position thereof and that fixes the upper structural body in a detachable manner.

Abstract: The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof.Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide.In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.

Abstract: The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof.Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide.In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.