Patents by Inventor Junichi Machida

Junichi Machida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7656202
    Abstract: A driving device and driving method for controlling electric power to a load is provided. The driving device controls switching operations of switching elements by setting a first duration in which electric power is supplied to the load and by setting a second duration in which the load is floated without electric power. The driving device feeds back an output signal outputted from output terminals of the load, receives an input signal, and compares the fed back output signal with the input signal to detect an error. The driving device also generates an error suppression signal to correct the detected error and controls the switching operation of the switching elements based on the error suppression signal.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: February 2, 2010
    Assignee: Asahi Kasei EMD Corporation
    Inventors: Toshio Kaiho, Junichi Machida
  • Patent number: 7463090
    Abstract: Output signal waveform having high input signal reproducibility is outputted from inductive load or the like. Output signals V1a and V1b obtained by feeding back an output signal Vp-n1 at output terminals 50 and 51 across load L1 to input terminals 9a and 9b are compared with an input signal Vin to detect an error between signals; a first error suppression signal Vout1 is produced such that the detected error between the signals is suppressed; inclination of first error suppression signal Vout1 is detected, and a second error suppression signal Vout2 is produced such that inclination error to input signal Vin is suppressed based on the detected inclination signal; and the ratio between the period that electric power is supplied to the load L1 and the period that electric power is not supplied to the load L1 is modified according to the error of the error suppression signal.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: December 9, 2008
    Assignee: Asahi Kasei EMD Corporation
    Inventors: Toshio Kaiho, Junichi Machida
  • Publication number: 20070290726
    Abstract: A waveform of the output signal having high reproducibility to an input signal is outputted from capacitive load. Even the driving device is configured as a switching amplifier and drives capacitive load. Reactive power can be reduced to perform low power consumption. Output signals V1a and V1b that an output signal Vcap1 across output terminals 50 and 51 of load C1 fed back to input terminals 9a and 9b are compared with an input signal Vin so that error between output signals V1a and V1b is detected. A first error suppression signal Vout1 is produced so as to suppress the detected error between signals. The proportion of a first duration T1 that electric power is supplied to the load C1 to a second duration T2 that no electric power is supplied and load C1 is floated is altered according to the first error suppression signal.
    Type: Application
    Filed: May 15, 2007
    Publication date: December 20, 2007
    Inventors: Toshio Kaiho, Junichi Machida
  • Publication number: 20070273437
    Abstract: Output signal waveform having high input signal reproducibility is outputted from inductive load or the like. Output signals V1a and V1b obtained by feeding back an output signal Vp-n1 at output terminals 50 and 51 across load L1 to input terminals 9a and 9b are compared with an input signal Vin to detect an error between signals; a first error suppression signal Vout1 is produced such that the detected error between the signals is suppressed; inclination of first error suppression signal Vout1 is detected, and a second error suppression signal Vout2 is produced such that inclination error to input signal Vin is suppressed based on the detected inclination signal; and the ratio between the period that electric power is supplied to the load L1 and the period that electric power is not supplied to the load L1 is modified according to the error of the error suppression signal.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 29, 2007
    Inventors: Toshio Kaiho, Junichi Machida
  • Patent number: 5960159
    Abstract: A substrate processing apparatus includes a substrate supporting pedestal having an upper substrate supporting pedestal and a lower substrate supporting pedestal which are vertically stacked, an upper resistance heater provided above the upper substrate supporting pedestal so as to be opposite to the upper substrate supporting pedestal, and a lower resistance heater provided under the lower substrate supporting pedestal so as to be opposite to the lower substrate supporting pedestal. Each of the upper substrate supporting pedestal and the lower substrate supporting pedestal is capable of mounting a substrate or substrates in a substantially horizontal position, and the lower substrate supporting pedestal including an opening which exposes the substrate in its entirety or openings which expose the substrates in their entireties as viewed from under the lower substrate supporting pedestal.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: September 28, 1999
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Fumihide Ikeda, Junichi Machida, Masayuki Tomita, Yasuhiro Inokuchi, Kazuhiro Shimeno, Hisashi Nomura, Tetsuaki Inada
  • Patent number: 5835076
    Abstract: A pen input liquid crystal display has row electrodes, column electrodes orthogonal to the row electrodes, and a liquid crystal layer interposed between the row and column electrodes. A pen input detecting signal is applied to one of the column electrodes, and display signals to the other column electrodes. The column electrode that receives the pen input detecting signal is sequentially shifted among the column electrodes, to simultaneously carry out a pen input scanning operation and an image displaying operation.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: November 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Machida, Nobuyuki Kawano, Takeshi Suyama
  • Patent number: 5723986
    Abstract: A level shifting circuit has a high-level shifter connected to a first high voltage and to a first low voltage, for amplifying the peak voltage of an input signal; a low-level shifter connected to a second high voltage lower than the first high voltage and to a second low voltage lower than the first low voltage, for amplifying the trough voltage of the input signal; a high-voltage controlling transistor connected to the first high voltage and to an output node and turned on and off according to the output of the high-level shifter; and a low-voltage controlling transistor connected to the output node and to the second low voltage and turned on and off according to the output of the low-level shifter complementarily to the high-voltage controlling transistor. The level shifting circuit is capable of amplifying both the peak and trough voltages of an input signal.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: March 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Nakashiro, Isao Abe, Takeshi Suyama, Junichi Machida