Abstract: A wafer for mounting substrates according to the present disclosure includes a multilayer ceramic substrate including top face electrodes, bottom face electrodes, and internal electrodes providing connection between the top face electrodes and the bottom face electrodes, and a wiring pattern formed on a top face of the multilayer ceramic substrate. The wiring pattern has a minimum line width which is equal to or less than 2 ?m and a minimum line space which is equal to or less than 2 ?m. When the wafer for mounting substrates is zoned into a plurality of regions by the units of 20 mm×20 mm, at least 50% of the regions satisfy the condition that an SFQR in 20 mm×20 mm evaluation region be equal to or less than 2 ?m, at the top face of the multilayer ceramic substrate.

Abstract: A method of producing a multi-layer ceramic substrate includes the steps of: (A) preparing a first ceramic green sheet with a thermal expansion layer arranged thereon, and at least one second ceramic green sheet with no thermal expansion layer arranged thereon; (B) laminating the first and second ceramic green sheets with the thermal expansion layer sandwiched therebetween, thereby obtaining a green sheet laminate; (C) pressure-bonding together the ceramic green sheets of the green sheet laminate; (D) heating and thereby expanding the thermal expansion layer in the pressure-bonded green sheet laminate; (E) extracting a portion of the green sheet laminate that has been displaced the expansion of the thermal expansion layer, thereby forming a cavity in the green sheet laminate; and (F) sintering the green sheet laminate with the cavity formed therein.

Abstract: Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein Young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than Young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit.

Abstract: A wafer for mounting substrates according to the present disclosure includes a multilayer ceramic substrate including top face electrodes, bottom face electrodes, and internal electrodes providing connection between the top face electrodes and the bottom face electrodes, and a wiring pattern formed on a top face of the multilayer ceramic substrate. The wiring pattern has a minimum line width which is equal to or less than 2 ?m and a minimum line space which is equal to or less than 2 ?m. When the wafer for mounting substrates is zoned into a plurality of regions by the units of 20 mm×20 mm, at least 50% of the regions satisfy the condition that an SFQR in 20 mm×20 mm evaluation region be equal to or less than 2 ?m, at the top face of the multilayer ceramic substrate.

Abstract: Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein Young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than Young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit.

Abstract: Disclosed is a dielectric ceramic composition which has high dielectric constant and suppressed low thermal expansion coefficient. Also disclosed are a multilayer dielectric substrate using the dielectric ceramic composition, and an electronic component. Specifically disclosed is a dielectric ceramic composition which contains an ATiO3 (wherein A represents either Ca and/or Sr) phase and an AAl2Si2O8 phase, said dielectric ceramic composition being characterized in that the dielectric constant is not less than 10 at 3 GHz and the average thermal expansion coefficient over the temperature range of 40-600° C. is less than 7 ppm/° C.

Abstract: Disclosed is a dielectric ceramic composition which has high dielectric constant and suppressed low thermal expansion coefficient. Also disclosed are a multilayer dielectric substrate using the dielectric ceramic composition, and an electronic component. Specifically disclosed is a dielectric ceramic composition which contains an ATiO3 (wherein A represents either Ca and/or Sr) phase and an AAl2Si2O8 phase, said dielectric ceramic composition being characterized in that the dielectric constant is not less than 10 at 3 GHz and the average thermal expansion coefficient over the temperature range of 40-600° C. is less than 7 ppm/° C.

Abstract: A coating apparatus comprises an upstream lip and a downstream lip defining a slot between the two lips through which a coating liquid can be extruded; and a pair of guide rollers disposed on opposite side of the lips for guiding a support to move past the lips such that the coating liquid can be applied thereto, wherein the downstream lip has a coating operation surface facing and curved toward the support and, a curvature k of the curved coating operation surface being given asP.sub.2 /T.ltoreq.k.ltoreq.P.sub.1 /Twhere T represents the tension in the coated portion of the support, and P.sub.1 and P.sub.2 represent the pressures of the coating liquid acting on the support at upstream and downstream ends of said coating operation surface.

Abstract: A coating apparatus comprises an upstream lip and a downstream lip defining a slot between the two lips through which a coating liquid can be extruded; and a pair of guide rollers disposed on opposite side of the lips for guiding a support to move past the lips such that the coating liquid can be applied thereto, wherein the downstream lip has a coating operation surface facing and curved toward the support and, a curvature k of the curved coating operation surface being given asP.sub.2 /T.ltoreq.k.ltoreq.P.sub.1 /Twhere T represents the tension in the coated portion of the support, and P.sub.1 and P.sub.2 represent the pressures of the coating liquid acting on the support at upstream and downstream ends of said coating operation surface.