Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: A balancer of an engine includes a rod and a balancer piston. A first end portion of the rod includes a joining portion which is arranged to be joined to a crankshaft of the engine at a position that is eccentric relative to a rotation axis of the crankshaft. A second end portion of the rod is arranged to reciprocate inside a cylinder according to a rotation of the crankshaft. The balancer piston is fixed to the second end portion of the rod. The balancer piston is arranged to reciprocate inside the cylinder, while rocking between a contact state in which the balancer piston is in contact with an inner wall surface of the cylinder and a non-contact state in which the balancer piston is separated from the inner wall surface. The balancer piston includes a cylindrical outer peripheral portion that is curved so as to swell toward the inner wall surface.

Abstract: A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

Abstract: A balancer of an engine includes a rod and a balancer piston. A first end portion of the rod includes a joining portion which is arranged to be joined to a crankshaft of the engine at a position that is eccentric relative to a rotation axis of the crankshaft. A second end portion of the rod is arranged to reciprocate inside a cylinder according to a rotation of the crankshaft. The balancer piston is fixed to the second end portion of the rod. The balancer piston is arranged to reciprocate inside the cylinder, while rocking between a contact state in which the balancer piston is in contact with an inner wall surface of the cylinder and a non-contact state in which the balancer piston is separated from the inner wall surface. The balancer piston includes a cylindrical outer peripheral portion that is curved so as to swell toward the inner wall surface.

Abstract: A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: The semiconductor device comprises a first conductive pattern 42, a second conductive pattern 42 formed adjacent to the first conductive pattern 42, a first conductor plug 28 formed below a prescribed region of the first conductive pattern 42, a second conductor plug 62n formed over a prescribed region of the first conductive pattern 42, a third conductor plug 28 formed below a prescribed region of the second conductive pattern 42, which is adjacent to a prescribed region of the first conductive pattern 42, a fourth conductor plug 62n+1 formed over a prescribed region of the second conductive pattern 42, a third conductive pattern 64 formed above the first conductive pattern 42 and connected to the second conductor plug 62a, and a fourth conductive pattern 64 formed above the second conductive pattern 42 and connected to the fourth conductor plug 62. The fourth conductor plug 62n+1 is arranged a position which is offset from the second conductor plug 62n.

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: The semiconductor device comprises a first conductive pattern 42, a second conductive pattern 42 formed adjacent to the first conductive pattern 42, a first conductor plug 28 formed below a prescribed region of the first conductive pattern 42, a second conductor plug 62n formed over a prescribed region of the first conductive pattern 42, a third conductor plug 28 formed below a prescribed region of the second conductive pattern 42, which is adjacent to a prescribed region of the first conductive pattern 42, a fourth conductor plug 62n+1formed over a prescribed region of the second conductive pattern 42, a third conductive pattern 64 formed above the first conductive pattern 42 and connected to the second conductor plug 62a, and a fourth conductive pattern 64 formed above the second conductive pattern 42 and connected to the fourth conductor plug 62. The fourth conductor plug 62n+1 is arranged a position which is offset from the second conductor plug 62n.

Abstract: The semiconductor device includes a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract: The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42.

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract: The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration.