Patents by Inventor Junichi Murota

Junichi Murota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210276451
    Abstract: A battery system includes a nickel-metal hydride battery and an ECU that controls charging and discharging of the nickel-metal hydride battery. The ECU calculates a discharge electricity amount showing an integrated value of a current discharged from the nickel-metal hydride battery, and further calculates ?SOC of the nickel-metal hydride battery in a prescribed time period. The ECU calculates a charge reserve capacity of the nickel-metal hydride battery based on a temperature of the nickel-metal hydride battery, the discharge electricity amount, and the ?SOC.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 9, 2021
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, PRIMEARTH EV ENERGY CO., LTD.
    Inventors: Takayuki IRIE, Jun SATOH, Junichi MATSUMOTO, Daisuke KOBA, Yosuke MUROTA, Kazuki NAKANO, Suguru MURAKI
  • Patent number: 6949474
    Abstract: This invention makes it possible to make even films composed of at least silicon and germanium with gradient germanium ratio along a film thickness direction thereof for a short deposition time. A temperature controller 61 controls a heater 2 so that temperature of wafers W will be changed from low (e.g. 400° C.) to high (e.g. 700° C.) by alternately repeating temperature changing process to heat up the wafers W and temperature regulating process when temperature of the wafers W does not change as much as that of the temperature changing process for a specific amount of time. While a gas controller 62 provides a reactive gas into a reaction tube 1 during the temperature regulating process, it controls a valve 31 to stop it during the temperature changing process.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: September 27, 2005
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Yasuo Kunii, Junichi Murota
  • Patent number: 6800544
    Abstract: A metal-semiconductor junction comprising a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: President of Tohoku University
    Inventors: Junichi Murota, Yosuke Shimamune, Masao Sakuraba, Takashi Matsuura
  • Patent number: 6770507
    Abstract: There is provided a novel bonded semiconductor wafer having a layered structure alternately stacked with semiconductor layers and insulator layers in two cycles or more and manufactured by means of a bonding process, wherein at least one of the insulator layers is formed with ion implanted oxygen, and a novel manufacturing process for a bonded semiconductor wafer in which an ion implantation separation process is adopted. The novel bonded semiconductor wafer is manufactured by means of a bonding process and has a layered structure alternately stacked with semiconductor layers and insulator layers in two cycles or more, wherein at least one of the insulator layers is formed with ion implanted oxygen.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: August 3, 2004
    Assignee: Shin-Etsu Handotai Co., LTD
    Inventors: Takao Abe, Takashi Matsuura, Junichi Murota
  • Publication number: 20040033686
    Abstract: A metal-semiconductor junction comprising a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n -or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.
    Type: Application
    Filed: August 19, 2002
    Publication date: February 19, 2004
    Inventors: Junichi Murota, Yosuke Shimamune, Masao Sakuraba, Takashi Matsuura
  • Publication number: 20040007185
    Abstract: This invention makes it possible to make even films composed of at least silicon and germanium with gradient germanium ratio along a film thickness direction thereof for a short deposition time. A temperature controller 61 controls a heater 2 so that temperature of wafers W will be changed from low (e.g. 400° C.) to high (e.g. 700° C.) by alternately repeating temperature changing process to heat up the wafers W and temperature regulating process when temperature of the wafers W does not change as much as that of the temperature changing process for a specific amount of time. While a gas controller 62 provides a reactive gas into a reaction tube 1 during the temperature regulating process, it controls a valve 31 to stop it during the temperature changing process.
    Type: Application
    Filed: February 6, 2003
    Publication date: January 15, 2004
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Yasuo Kunii, Junichi Murota
  • Patent number: 6621145
    Abstract: A metal-semiconductor junction comprises a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: September 16, 2003
    Assignee: President of Tohoku University
    Inventors: Junichi Murota, Yosuke Shimamune, Masao Sakuraba, Takashi Matsuura
  • Publication number: 20020182827
    Abstract: There is provided a novel bonded semiconductor wafer having a layered structure alternately stacked with semiconductor layers and insulator layers in two cycles or more and manufactured by means of a bonding process, wherein at least one of the insulator layers is formed with ion implanted oxygen, and a novel manufacturing process for a bonded semiconductor wafer in which an ion implantation separation process is adopted. The novel bonded semiconductor wafer is manufactured by means of a bonding process and has a layered structure alternately stacked with semiconductor layers and insulator layers in two cycles or more, wherein at least one of the insulator layers is formed with ion implanted oxygen.
    Type: Application
    Filed: September 20, 2001
    Publication date: December 5, 2002
    Inventors: Takao Abe, Takashi Matsuura, Junichi Murota
  • Publication number: 20020119663
    Abstract: A semiconductor material such as Si wafer with a fine structure (porous layer) formed, without using electrical current, on its surface by being contacted with a solution that contains fluoro-complex such as hexafluorotitanate.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 29, 2002
    Inventors: Takashi Matsuura, Junichi Murota, Mitsuo Miyamoto
  • Publication number: 20020109135
    Abstract: The MOS field-effect transistor aims to enhance the electron mobility and the hole mobility in the channel portion by employing the strained-Si/SiGe (or Si/SiGeC) structure. Crystallinity of such a heterostructure is maintained in a preferable state, shortening of the effective channel length is prevented, diffusion of Ge is prevented and the resistance of the source layer and the drain layer is reduced. The channel region has a layered structure formed by stacking the Si layer and, the SiGe or SiGeC layer in order from the surface. The source layer and the drain layer formed of SiGe or SiGeC including high concentration impurity atoms providing a desired conduction type, are in contact with both end surfaces of the channel region. The surfaces of the source layer and the drain layer have a shape rising upwardly from the bottom portion of the gate electrode.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 15, 2002
    Inventors: Junichi Murota, Masao Sakuraba, Takashi Matsuura, Toshiaki Tsuchiya
  • Publication number: 20020027285
    Abstract: A metal-semiconductor junction comprising a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.
    Type: Application
    Filed: May 30, 2001
    Publication date: March 7, 2002
    Inventors: Junichi Murota, Yosuke Shimamune, Masao Sakuraba, Takashi Matsuura
  • Publication number: 20020008289
    Abstract: A semiconductor device is disclosed which allows for ease of fabrication of CMOS LSI chips and is adapted to increase the mobility of electrons and holes. The semiconductor device comprises a substrate, an insulating layer formed over the substrate, and a stacked Si/SiGe/Si region comprising a first layer of Si, a layer of SiGe, and a second layer of Si which are sequentially formed in this order on the insulating layer. The topmost second layer of Si and the layer of SiGe are strained due to the difference in lattice constant between each layer in the stacked Si/SiGe/Si region. An n-MOSFET and a p-MOSFET are formed in the stacked region. The n-MOSFET has a surface channel consisting of the second Si layer, whereas the p-MOSFET has a double channel of a buried channel consisting of the SiGe layer and a surface channel consisting of the second Si layer.
    Type: Application
    Filed: July 20, 2001
    Publication date: January 24, 2002
    Inventors: Junichi Murota, Toshiaki Tsuchiya, Takashi Matsuura, Masao Sakuraba
  • Publication number: 20010016247
    Abstract: Disclosed is a method of manufacturing a laminate structure, comprising the steps of laminating a plurality of photosensitive material layers one upon the other to form a laminated photosensitive layer, the photosensitive characteristics of at least one of the photosensitive material layers differing from those of the other photosensitive material layers, applying a light exposure treatment to the laminated photosensitive layer a plurality of times under different light exposure conditions so as to transfer desired patterns to the plural photosensitive material layers, and developing the plural photosensitive material layers having the patterns transferred thereto.
    Type: Application
    Filed: January 2, 2001
    Publication date: August 23, 2001
    Applicant: TOHOKU UNIVERSITY
    Inventors: Takashi Matsuura, Junichi Murota
  • Patent number: 5705224
    Abstract: A vapor deposition apparatus and method in which pulse waveform light is applied to a sample sealed in a reaction chamber. The sample is exposed to gaseous material while the pulse waveform light is applied creating one or plural atomic layers. Alternate layers of plural substances or alternate multiple layers of plural substances can be formed by alternating the introduction of gaseous materials with the application of pulse waveform light.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: January 6, 1998
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Junichi Murota, Shoichi Ono, Masao Sakuraba, Nobuo Mikoshiba, Harushige Kurokawa, Fumihide Ikeda
  • Patent number: 4976815
    Abstract: A draft chamber is located within a clean room for sequentially immersing and processing carriers such as silicone wafers in a plurality of solution vessels provided in the draft chamber. In the draft chamber, a first air flow moves in a substantially horizontal direction from the front portion of the draft chamber toward the rear portion above the surfaces of solutions contained in chemical solution vessels which generate toxic gasses and a second air flow moves downward from the ceiling of the draft chamber. Thus, the toxic gasses generated from the chemical solution vessels are prevented from leaking into the clean room.
    Type: Grant
    Filed: October 25, 1989
    Date of Patent: December 11, 1990
    Assignees: Ohmi Tadahiro, Hitachi Plant Engineering & Construction Co., Ltd.
    Inventors: Yutaka Hiratsuka, Tadahiro Ohmi, Junichi Murota, Yoshio Fujisaki, Masato Noda, Yoshimitsu Kitada, Terutaka Sahara
  • Patent number: 4503807
    Abstract: A chemical vapor deposition apparatus has a reactor divided into a reaction space and a purging space by a susceptor for supporting a wafer and a loading chamber communicated through a gate with the reactor. Exhaust units are communicated with the reactor and loading chamber, respectively, so that the pressures in the reactor and loading chamber may be reduced. The susceptor has a plurality of recesses to aid placing or scooping the water. Through a transparent wall on the side of the purging space, the susceptor is heated by a lamp unit disposed outside the transparent wall. The loading chamber includes a wafer transport mechanism for charging a wafer into the reactor or discharging a processed wafer from the reactor. An unprocessed wafer is loaded to the loading chamber from a cassette and the processed wafer is unloaded to the cassette. One or a small number of wafers are processed at one time. A uniform film is deposited with a high reproducibility.
    Type: Grant
    Filed: May 29, 1984
    Date of Patent: March 12, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Satoshi Nakayama, Hideaki Takeuchi, Junichi Murota, Tatuhiko Hurukado, Shigeru Takeda, Masuo Suzuki, Harushige Kurokawa, Humihide Ikeda
  • Patent number: 4146902
    Abstract: A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage. A semiconductor memory device is constituted by using the switching element as a memory cell and a semiconductor gate element for controlling the current flowing through the semiconductor switching element.
    Type: Grant
    Filed: June 20, 1978
    Date of Patent: March 27, 1979
    Assignee: Nippon Telegraph and Telephone Public Corp.
    Inventors: Masafumi Tanimoto, Takashi Watanabe, Nobuaki Ieda, Junichi Murota
  • Patent number: 4074300
    Abstract: In an insulated gate type field effect transistor comprising spaced source and drain regions, an insulating film between the source and drain regions and a gate electrode mounted on the insulating film, an inverted frustum shaped polycrystalline semiconductor layer is formed on the insulating film and the gate electrode is mounted on the polycrystalline semiconductor layer.
    Type: Grant
    Filed: February 13, 1976
    Date of Patent: February 14, 1978
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Tetsushi Sakai, Yutaka Sakakibara, Junichi Murota, Tsutomu Wada