Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N?1) variable delay circuit that adjusts delay time for at least (N?1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N?1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N?1) variable delay circuit that adjusts delay time for at least (N?1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N?1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: It is intended to provide an AD converter capable of increasing its conversion accuracy. An AD converter is equipped with a clock generator which generates a first clock using a second clock and a comparator which includes a comparison circuit for comparing an input signal with a prescribed value in a first period of the first clock and a precharging circuit for precharging, in a second period of the first clock, an internal voltage to a prescribed value for the next comparison operation. The clock generator includes a replica circuit of the precharging circuit of the comparator. In the replica circuit of the precharging circuit, a precharging period from the start to the end of precharging is set as the second period of the first clock.

Abstract: It is intended to provide an AD converter capable of increasing its conversion accuracy. An AD converter is equipped with a clock generator which generates a first clock using a second clock and a comparator which includes a comparison circuit for comparing an input signal with a prescribed value in a first period of the first clock and a precharging circuit for precharging, in a second period of the first clock, an internal voltage to a prescribed value for the next comparison operation. The clock generator includes a replica circuit of the precharging circuit of the comparator. In the replica circuit of the precharging circuit, a precharging period from the start to the end of precharging is set as the second period of the first clock.

Abstract: Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.

Abstract: A parallel interpolation A/D converter includes a reference voltage generation circuit configured to generate (m+1) different reference voltages VR1-VRm+1, where m is a positive integer, and VR1<VR2, . . . , <VRm<VRm+1, a differential amplifier series including (m+1) differential amplifiers A1-Am+1 configured to amplify voltage differences between the reference voltages VR1-VRm+1 and an input signal voltage, and an operation circuit including a plurality of comparator circuits configured to receive output voltage sets generated by the respective differential amplifiers. The number of comparator circuits varies depending on the value k of the reference voltage VRk, where k is an integer of 2?k?m+1.

Abstract: Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.

Abstract: A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.

Abstract: A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.

Abstract: A full-flash A/D converter, including a differential amplifier circuit row and a voltage comparison circuit row, has an adjusting circuit 107 for making the output dynamic range of differential amplifier circuits accurately fall within the input dynamic range of voltage comparison circuits. The adjusting circuit 107 includes a reference voltage generation circuit 119, which has therein voltage generation circuits 122 whose resistors are connected in series. By this series connection, the area of the voltage generation circuits 122 is reduced, while the output dynamic range of the differential amplifier circuits A1 to Am+1 in the differential amplifier circuit row 102 accurately falls within the input dynamic range of the voltage comparison circuits Cr1 to Crm+1 in the voltage comparison circuit row 103. Furthermore, half-circuits in the voltage generation circuits 122 are used to generate reference voltages, whereby the area of the voltage generation circuits is reduced further.

Abstract: A full-flash A/D converter, including a differential amplifier circuit row and a voltage comparison circuit row, has an adjusting circuit 107 for making the output dynamic range of differential amplifier circuits accurately fall within the input dynamic range of voltage comparison circuits. The adjusting circuit 107 includes a reference voltage generation circuit 119, which has therein voltage generation circuits 122 whose resistors are connected in series. By this series connection, the area of the voltage generation circuits 122 is reduced, while the output dynamic range of the differential amplifier circuits A1 to Am+1 in the differential amplifier circuit row 102 accurately falls within the input dynamic range of the voltage comparison circuits Cr1 to Crm+1 in the voltage comparison circuit row 103. Furthermore, half-circuits in the voltage generation circuits 122 are used to generate reference voltages, whereby the area of the voltage generation circuits is reduced further.

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.

Abstract: In an A/D converter, each preamp 102 includes a preamp gain adjusting circuit 109. The preamp gain adjusting circuit 109 suppresses the gain of the preamp 102 and restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preamp 102 exceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.

Abstract: In an A/D converter, each preamp 102 includes a preamp gain adjusting circuit 109. The preamp gain adjusting circuit 109 suppresses the gain of the preamp 102 and restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preamp 102 exceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.

Abstract: As shown in FIG. 1, a gate terminal of a MOS transistor or an input terminal of a logic gate, which are included in a through current detection target net list, are extracted, and a resistor is inserted between the gate terminal of the MOS transistor or the input terminal of the logic gate and a power supply, and between the gate terminal of the MOS transistor or the input terminal of the logic gate and a reference voltage, respectively, thereby to perform net list conversion, and thereafter, DC analysis is executed. Therefore, a MOS transistor in which through current might occur can be detected, leading to reliable detection of through current that cannot be easily detected by the conventional DC analysis simulation, and reliable detection of a transistor in which through current might occur, in the through current detection target circuit.