Patents by Inventor Junichi SAIJO

Junichi SAIJO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and wire bonding method
    Patent number: 11749634
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a wire extending between the first electrode and the second electrode. The wire includes a first conductor in contact with the first electrode and the second electrode, and a second conductor that is provided inside the first conductor and has no contact with the first electrode and the second electrode.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Kazuya Maruyama, Tsutomu Sano, Junichi Saijo
  • SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD
    Publication number: 20210210457
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a wire extending between the first electrode and the second electrode. The wire includes a first conductor in contact with the first electrode and the second electrode, and a second conductor that is provided inside the first conductor and has no contact with the first electrode and the second electrode.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 8, 2021
    Applicant: Kioxia Corporation
    Inventors: Kazuya MARUYAMA, Tsutomu SANO, Junichi SAIJO
  • Semiconductor device and manufacturing method thereof
    Patent number: 9263418
    Abstract: According to one embodiment, a semiconductor device includes a first loop and a second loop. A folded-back portion is a portion formed by stretching out the first loop from a first bond in a first direction and then folding it back in a second direction. The folded-back portion is in a shape in which it is squashed against the first bond. The second loop is bonded to the folded-back portion. An end of the second loop is located at a second position. The second position is offset in a direction in which the first loop extends, from a first position. The first position is the center of the first bond of the first loop.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Kasuya, Junichi Saijo
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150262969
    Abstract: According to one embodiment, a semiconductor device includes a first loop and a second loop. A folded-back portion is a portion formed by stretching out the first loop from a first bond in a first direction and then folding it back in a second direction. The folded-back portion is in a shape in which it is squashed against the first bond. The second loop is bonded to the folded-back portion. An end of the second loop is located at a second position. The second position is offset in a direction in which the first loop extends, from a first position. The first position is the center of the first bond of the first loop.
    Type: Application
    Filed: September 12, 2014
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka KASUYA, Junichi SAIJO