Patents by Inventor Jun-ichi Shiozawa

Jun-ichi Shiozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6369423
    Abstract: The present invention intends to provide a semiconductor device capable of realizing a thin gate stack and the manufacturing method thereof. A gate cap layer and/or a protection insulating film (an etching stopper) has a plurality of insulating materials such as oxide and nitride stacked on each other. With this structure, an insulating layer having an etching rate lower than that of the interlayer insulating layer, for example, can be exposed during the etching of the interlayer insulating layer, and the gate stack can be formed thin and the aspect ratio of the contact hole formed in the device can be reduced. The present invention can realize a thin gate stack in such a manner, and thus is suitable for a SAC used in a DRAM.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: April 9, 2002
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Tokuhisa Ohiwa, Jeffrey P. Gambino, Katsuya Okumura, Jun-ichi Shiozawa
  • Publication number: 20020014657
    Abstract: The present invention intends to provide a semiconductor device capable of realizing a thin gate stack and the manufacturing method thereof. A gate cap layer and/or a protection insulating film (an etching stopper) has a plurality of insulating materials such as oxide and nitride stacked on each other. With this structure, an insulating layer having an etching rate lower than that of the interlayer insulating layer, for example, can be exposed during the etching of the interlayer insulating layer, and the gate stack can be formed thin and the aspect ratio of the contact hole formed in the device can be reduced. The present invention can realize a thin gate stack in such a manner, and thus is suitable for a SAC used in a DRAM.
    Type: Application
    Filed: March 3, 1998
    Publication date: February 7, 2002
    Inventors: TOKUHISA OHIWA, JEFFREY GAMBINO, KATSUYA OKUMURA, JUN-ICHI SHIOZAWA
  • Patent number: 6091117
    Abstract: A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: July 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5970352
    Abstract: A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: October 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5888876
    Abstract: A method of filling one or more trenches formed in a silicon substrate includes the steps of forming a thin polycrystalline silicon film in a trench such that the thin polycrystalline silicon film is sufficiently thin so as to not close the trench; forming an amorphous silicon film on thin polycrystalline film and the surface of the substrate and in the trenches; and annealing the amorphous silicon film such that the amorphous silicon layer migrates to fill the trenches to a first level. The deposition and annealing steps are performed in ambient atmospheres having low partial pressures of H.sub.2 O and O.sub.2, the annealing temperature is higher than the deposition temperature, and the annealing pressure is greater than the deposition pressure.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5451809
    Abstract: A semiconductor device has a substrate and a trench formed therein, the semiconductor device including a dielectric formed on the surface of the trench, a first amorphus silicon film formed on the dielectric film, a dopant film, a second amorphus silicon film, and a capping film formed between the dopant film and one of the first and second amorphus silicon films, the dopant film being formed between the other of the first and second amorphus silicon films and the capping film. The capping film is formed from one of silicon oxide and silicon nitride.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: September 19, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima