Patents by Inventor Junichi Tatsuda

Junichi Tatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, method and computer program product for timing-independent sequential equivalence verification
    Patent number: 7607115
    Abstract: A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to generate output. To this end, sequential equivalence of the first system and the second system may be verified, based on the output.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: October 20, 2009
    Assignee: Calypto Design Systems, Inc.
    Inventors: Venkatram Krishnaswamy, Shusaku Yamamoto, Junichi Tatsuda