Patents by Inventor Junichi Tsuda
Junichi Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11488896Abstract: An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.Type: GrantFiled: September 28, 2015Date of Patent: November 1, 2022Assignee: Mitsubishi Electric CorporationInventors: Yukimasa Hayashida, Shigeru Hasegawa, Ryo Tsuda, Ryutaro Date, Junichi Nakashima
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Patent number: 9893509Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.Type: GrantFiled: December 29, 2015Date of Patent: February 13, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Mochikawa, Atsuhiko Kuzumaki, Junichi Tsuda, Yushi Koyama
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Publication number: 20160134098Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.Type: ApplicationFiled: December 29, 2015Publication date: May 12, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi MOCHIKAWA, Atsuhiko KUZUMAKI, Junichi TSUDA, Yushi KOYAMA
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Patent number: 9257248Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.Type: GrantFiled: November 27, 2012Date of Patent: February 9, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Mochikawa, Atsuhiko Kuzumaki, Junichi Tsuda, Yushi Koyama
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Patent number: 8514596Abstract: The present invention includes: an inverter 1 configured to perform pulse wide modulation on an output from a DC power source 5; a first capacitor pair 41 provided at an input side of the inverter and including two capacitors serially connected to form a neutral point; a second capacitor pair 42 provided at an output side of the inverter and including two capacitors serially connected to form a neutral point; a bypass path g for a leakage current formed by connecting the neutral point of the first capacitor pair and the neutral point of the second capacitor pair to each other; at least one common mode choke coil 3 provided between the first capacitor pair and the second capacitor pair and configured to suppress a common mode current generated in the inverter; and an output filter 2 configured to convert a voltage, which is outputted from the inverter and subjected to the pulse wide modulation, into a voltage in a sine wave form.Type: GrantFiled: July 21, 2009Date of Patent: August 20, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yushi Koyama, Junichi Tsuda, Hiroshi Mochikawa
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Patent number: 8472215Abstract: According to one embodiment, a grid-tie inverter includes: a inverter performing pulse width modulation for a DC voltage; a first capacitor circuit connected to an input side of the inverter so as to form a neutral point; a second capacitor circuit connected to an output side of the inverter so as to form a neutral point; a common mode current bypass channel formed by connecting the neutral points of the first capacitor circuit and the second capacitor circuit; a grounded capacitor provided between the bypass channel and a ground; a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit; and an output filter converting a pulse width-modulated voltage outputted from the inverter into a sine AC voltage.Type: GrantFiled: July 12, 2012Date of Patent: June 25, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yushi Koyama, Junichi Tsuda, Hiroshi Mochikawa
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Publication number: 20130134958Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.Type: ApplicationFiled: November 27, 2012Publication date: May 30, 2013Inventors: Hiroshi MOCHIKAWA, Atsuhiko KUZUMAKI, Junichi TSUDA, Yushi KOYAMA
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Publication number: 20120275201Abstract: According to one embodiment, a grid-tie inverter includes: a inverter performing pulse width modulation for a DC voltage; a first capacitor circuit connected to an input side of the inverter so as to form a neutral point; a second capacitor circuit connected to an output side of the inverter so as to form a neutral point; a common mode current bypass channel formed by connecting the neutral points of the first capacitor circuit and the second capacitor circuit; a grounded capacitor provided between the bypass channel and a ground; a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit; and an output filter converting a pulse width-modulated voltage outputted from the inverter into a sine AC voltage.Type: ApplicationFiled: July 12, 2012Publication date: November 1, 2012Inventors: Yushi KOYAMA, Junichi TSUDA, Hiroshi MOCHIKAWA
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Patent number: 8089780Abstract: A semiconductor switch is provided with a main element having reverse conductivity and serving as a voltage-driven switching element having a high withstand voltage, an auxiliary element serving as a voltage-driven switching element having a withstand voltage lower than that of the main element, and a high-speed freewheel diode having a withstand voltage equal to that of the main element, wherein a negative pole of the main element is connected to a negative pole of the auxiliary element to define the positive pole of the main element as a positive pole terminal and the positive pole of the auxiliary element as a negative pole terminal, and the high-speed freewheel diode is parallel-connected between the positive pole terminal and the negative pole terminal so that a direction from the negative pole terminal toward the positive pole terminal constitutes a forward direction.Type: GrantFiled: February 4, 2008Date of Patent: January 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Mochikawa, Tateo Koyama, Atsuhiko Kuzumaki, Junichi Tsuda
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Publication number: 20110216568Abstract: The present invention includes: an inverter 1 configured to perform pulse wide modulation on an output from a DC power source 5; a first capacitor pair 41 provided at an input side of the inverter and including two capacitors serially connected to form a neutral point; a second capacitor pair 42 provided at an output side of the inverter and including two capacitors serially connected to form a neutral point; a bypass path g for a leakage current formed by connecting the neutral point of the first capacitor pair and the neutral point of the second capacitor pair to each other; at least one common mode choke coil 3 provided between the first capacitor pair and the second capacitor pair and configured to suppress a common mode current generated in the inverter; and an output filter 2 configured to convert a voltage, which is outputted from the inverter and subjected to the pulse wide modulation, into a voltage in a sine wave form.Type: ApplicationFiled: July 21, 2009Publication date: September 8, 2011Inventors: Yushi Koyama, Junichi Tsuda, Hiroshi Mochikawa
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Publication number: 20100321966Abstract: A semiconductor switch is provided with a main element having reverse conductivity and serving as a voltage-driven switching element having a high withstand voltage, an auxiliary element serving as a voltage-driven switching element having a withstand voltage lower than that of the main element, and a high-speed freewheel diode having a withstand voltage equal to that of the main element, wherein a negative pole of the main element is connected to a negative pole of the auxiliary element to define the positive pole of the main element as a positive pole terminal and the positive pole of the auxiliary element as a negative pole terminal, and the high-speed freewheel diode is parallel-connected between the positive pole terminal and the negative pole terminal so that a direction from the negative pole terminal toward the positive pole terminal constitutes a forward direction.Type: ApplicationFiled: February 4, 2008Publication date: December 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Mochikawa, Tateo Koyama, Atsuhiko Kuzumaki, Junichi Tsuda
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Patent number: 6396723Abstract: There are provided: a main three-phase full-wave rectifier (8) that converts three-phase AC (R phase, S phase, T phase) into DC; a transformer (9) that outputs AC of a total of six phases corresponding to the points that equally divide by three the arcs drawn in a transformer vector diagram in which an equilateral triangle is formed whereof the R phase, S phase and T phase are vertices, centered on each vertex and linking the remaining two points; and two auxiliary three-phase full-wave rectifiers (12) and (13) in that convert into DC the six-phase AC that is output from the transformer (9), the output lines of the main three-phase full-wave rectifier (8) and two auxiliary three-phase full-wave rectifiers (12) and (13) being connected in parallel. The current flowing in the DC line through the transformer can therefore be reduced to ⅓ of the whole in the case of an 18-pulse rectifier, so enabling the capacity of the transformer to be reduced.Type: GrantFiled: June 15, 2001Date of Patent: May 28, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Mochikawa, Junichi Tsuda
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Publication number: 20020015320Abstract: There are provided: a main three-phase full-wave rectifier (8) that converts three-phase AC (R phase, S phase, T phase) into DC; a transformer (9) that outputs AC of a total of six phases corresponding to the points that equally divide by three the arcs drawn in a transformer vector diagram in which an equilateral triangle is formed whereof the R phase, S phase and T phase are vertices, centered on each vertex and linking the remaining two points; and two auxiliary three-phase full-wave rectifiers (12) and (13) that convert into DC the six-phase AC that is output from the transformer (9), the output lines of the main three-phase full-wave rectifier (8) and two auxiliary three-phase full-wave rectifiers (12) and (13) being connected in parallel. The current flowing in the DC line through the transformer can therefore be reduced to ⅓ of the whole in the case of an 18-pulse rectifier, so enabling the capacity of the transformer to be reduced.Type: ApplicationFiled: June 15, 2001Publication date: February 7, 2002Inventors: Hiroshi Mochikawa, Junichi Tsuda
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Patent number: 6036550Abstract: A connector holder (1) has an elongate front wall (2), an elongate and partitioning center wall (3) formed integral with, perpendicular to and along the inner edge of the front wall, and end walls (4, 4') extending perpendicular to the center wall and located at opposite ends of same. The end walls have latch means (6, 7 and 8) for engagement with the connectors of the pressure contacting type. A pair of spaces (5) for receiving the connectors are provided such that a side of each space facing the front wall is opened, with another side confronting the center wall also opened. The connector holder (1) further has lugs (11) that are capable of engaging with the entrances (26) of compartments formed in each connector (20), so that the electric wires received in the compartments are surely held in place.Type: GrantFiled: February 24, 1998Date of Patent: March 14, 2000Assignee: Japan Solderless Terminal Manufacturing Co., Ltd.Inventors: Masato Naganawa, Yutaka Ushiro, Junichi Tsuda
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Patent number: 5745784Abstract: A method for changing an external storage medium, in an information processing system including an electronic apparatus and at least one external storage medium linked to the electronic apparatus, comprises the steps of: providing an internal storage in the electronic apparatus; delivering a control operation from the electronic apparatus to the external storage medium; copying all processes including a preceding process, a main process and a following process, these being stored in the external storage medium, to the electronic apparatus, the preceding process being necessary to start the main process, and the following process being necessary to complete of the main process; starting an internal program in the internal storage in the electronic apparatus, moving an attribute text indicating a mounting process from the electronic apparatus to the external storage medium by using the internal program on the internal storage; executing the preceding process, the main process and the following process in accordType: GrantFiled: March 3, 1995Date of Patent: April 28, 1998Assignee: Fujitsu LimitedInventor: Junichi Tsuda
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Patent number: 5371749Abstract: An apparatus for preventing an error operation when withdrawing a part from a panel of an electronic apparatus which includes an abnormal state detecting unit for detecting an abnormal state of the part, a latching mechanism for preventing withdrawal of the part from the panel when the abnormal state detecting unit detects that the part is not abnormal and a latch releasing mechanism for releasing a latch for the part when the abnormal state detecting unit detects that the part is abnormal, whereby a system down state can be prevented.Type: GrantFiled: December 23, 1991Date of Patent: December 6, 1994Assignee: Fujitsu LimitedInventor: Junichi Tsuda