Patents by Inventor Junichi Udomoto

Junichi Udomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10511267
    Abstract: A multifinger transistor in which source fingers (201 to 206) and drain fingers (301 to 305) are arranged alternately with each of gate fingers (101 to 110) being sandwiched between one of the source fingers and one of the drain fingers is used. Line (10) and line (20) are attached to the source fingers (201 to 206) in an area on a gate side and causing a phase rotation such that the nearer to a central part a gate finger is, the more inductive the gate finger is.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuma Torii, Koji Yamanaka, Masaki Kono, Junichi Udomoto
  • Publication number: 20180316315
    Abstract: A multifinger transistor in which source fingers (201 to 206) and drain fingers (301 to 305) are arranged alternately with each of gate fingers (101 to 110) being sandwiched between one of the source fingers and one of the drain fingers is used. Line (10) and line (20) are attached to the source fingers (201 to 206) in an area on a gate side and causing a phase rotation such that the nearer to a central part a gate finger is, the more inductive the gate finger is.
    Type: Application
    Filed: December 8, 2015
    Publication date: November 1, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuma TORII, Koji YAMANAKA, Masaki KONO, Junichi UDOMOTO
  • Patent number: 9543902
    Abstract: A power amplifier includes: an amplifier; an input matching circuit connected to an input of the amplifier; an output matching circuit connected to an output of the amplifier; and a low-frequency processing circuit connected to the input matching circuit or the output matching circuit, wherein the low-frequency processing circuit includes a first line having a first end connected to the input matching circuit or the output matching circuit, a first shot stub connected to a second end of the first line and including a second line and a first capacitor connected in series each other, and a second short stub connected to the second end of the first line in parallel with the first short stub and including a third line and a second capacitor which are connected in series each other, the first line has a length of ?/8, the second line has a length of ?/4, and the third line has a length of ?/8 with respect to a wavelength ? of a fundamental frequency.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 10, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Matsuzuka, Junichi Udomoto, Tetsuo Kunii, Hiromitsu Utsumi
  • Publication number: 20160285421
    Abstract: A power amplifier includes: an amplifier; an input matching circuit connected to an input of the amplifier; an output matching circuit connected to an output of the amplifier; and a low-frequency processing circuit connected to the input matching circuit or the output matching circuit, wherein the low-frequency processing circuit includes a first line having a first end connected to the input matching circuit or the output matching circuit, a first shot stub connected to a second end of the first line and including a second line and a first capacitor connected in series each other, and a second short stub connected to the second end of the first line in parallel with the first short stub and including a third line and a second capacitor which are connected in series each other, the first line has a length of ?/8, the second line has a length of ?/4, and the third line has a length of ?/8 with respect to a wavelength ? of a fundamental frequency.
    Type: Application
    Filed: October 29, 2015
    Publication date: September 29, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takayuki MATSUZUKA, Junichi UDOMOTO, Tetsuo KUNII, Hiromitsu UTSUMI
  • Patent number: 7391268
    Abstract: A power amplifying device includes a stabilizing circuit between an input terminal and an amplifier. The stabilizing circuit has a first line, a second line, and a third line. The first line is connected to the ground. The length of the first line is equal to or longer than three fourths of the wavelength of the operating frequency.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: June 24, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Junichi Udomoto
  • Publication number: 20070115064
    Abstract: A power amplifying device includes a stabilizing circuit between an input terminal and an amplifier. The stabilizing circuit has a first line, a second line, and a third line. The first line is connected to the ground. The length of the first line is equal to or longer than three fourths of the wavelength of the operating frequency.
    Type: Application
    Filed: June 6, 2006
    Publication date: May 24, 2007
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Junichi Udomoto
  • Patent number: 6303950
    Abstract: A field effect transistor (FET) having a stabilization circuit with a stabilization condition not affected by another circuit element, for example, a matching circuit. The stabilization circuit is pre-formed inside of the FET, thereby pre-stabilizing the FET in a frequency range in which a power amplifier is used.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: October 16, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hitoshi Kurusu, Junichi Udomoto
  • Patent number: 6020613
    Abstract: A semiconductor device includes a high-power output transistor chip in which transistor cells are connected in parallel, each transistor cell including stripe-shaped gate electrodes connected to a gate bus, stripe-shaped drain electrodes connected to a drain pad, and stripe-shaped source electrodes connected to a source pad, wherein the drain electrodes and the source electrodes are alternatingly arranged and pairs of source and drain electrodes face each other across one of the gate electrodes; and a resistor including a portion of the gate bus between adjacent transistor cells, for preventing oscillation between the adjacent transistor cells. Since the resistor serves as a loss component, oscillation due to an imbalance in characteristics between adjacent transistor cells is cancelled so that the synthesis efficiency of the transistor cells is improved.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: February 1, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junichi Udomoto, Makio Komaru