Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

Abstract: The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

Abstract: This invention relates to a storage device including a wireless unit which performs wireless communication with another device, a storage unit for storing data, a processor which transmits, based on a command from the device that has been received by communication through the wireless unit, data stored in the storage unit from the wireless unit to another device and stores data received by the wireless unit in the storage unit, and a battery which supplies power to the wireless unit, storage unit, and processor.

Abstract: A method and system for planarization is disclosed. The system includes a mask including a medium density, sub-resolution region which allows less than the full intensity of the exposing radiation through to a resist layer. By including multiple density regions, improved planarization can be achieved.

Abstract: The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

Abstract: A wiring layer of a semiconductor integrated circuit comprises a first conductive film made of a material containing Al. A material, which reacts with Al at a rate lower than that at which Ti reacts with Al, is provided on the first conductive film. A first barrier metal film is formed, and an interlayer insulating film is formed thereon. An opening is formed in the interlayer insulating film so as to expose the first barrier metal film. The opening is buried to form a second conductive film electrically connected to the first conductive film.

Abstract: The invention allows for measurement at the same density as an actual device pattern and measures the level of registration of actual patterns with precision. In the measurement of the invention, a first exposure process is performed on a first-level pattern and a second exposure process is then performed on a second-level pattern. After that, the patterns are developed and etched, thereby forming two patterns of different shapes. Next, the resistance between terminals of a pattern which are obtained by means of etching is measured through a four-point measurement. An amount of misregistration of the first-level pattern and the second-level pattern is calculated from the measured resistance.

Abstract: A method of forming a buried plate electrode for a trench capacitor of a semiconductor memory device is provided. Trenches are formed in a semiconductor substrate and a dopant source film is formed on the sidewalls and bottom walls of the trenches. A resist is formed on the dopant source film which fills in the trenches. The resist is recessed to remain in the trenches at a level which is below the surface of the semiconductor substrate. Impurities are implanted into the semiconductor substrate using the recessed resist as a block mask. The dopant source film is etched using the recessed resist as an etching mask and the recessed resist is then removed. The implanted impurities and dopants from the dopant source film are diffused into the semiconductor substrate to form a buried plate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

Abstract: The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.

Abstract: A method and system for planarization of a semiconductor wafer is disclosed. The disclosed system includes a mask with at least a medium density pattern, where the pattern dimensions are below the resolving power of an exposure system. Less than full intensity of the exposing radiation passes through the medium density pattern of the mask to a resist layer and does not completely expose the underlying resist. Through adapting at least a portion of the mask to account for surface irregularities of a wafer's surface, improved planarization of the surface is achieved.

Abstract: The method of measuring the aberration of the projection optics, according to the present invention includes the following steps. In the first step, the first mask pattern including the first pattern in which a line and space pattern is arranged on a photomask to be linearly symmetrical, and the second pattern in which line patterns having a large line width are arranged on outer sides of the first pattern, to be linearly symmetrical, is transferred on a substrate. In the second step, the second mask pattern in which a patter designed to leave a part of the first pattern and a pattern designed to leave the entire second pattern are arranged to be linearly symmetrical, is transferred on the same substrate, so as to superimpose it on the transferred first pattern. In the third step, the position of the transferred pattern of the second pattern, and the predetermined position of the pattern section of the transferred pattern of the first pattern, which is left in the second step are detected.

Abstract: A method of forming an opening in a first film is provided, wherein the opening has first and second opening portions and the first film is an insulating film. The first opening portion is formed in the first film and a second film is formed on an upper surface of the first film and to fill in the first opening portion. A masking film is formed on the second film. The first film and the second film are etched by a first etching process using the masking film as a mask to form the second opening portion. The first film and the second film are etched at substantially the same rate by the first etching process. The remaining portion of the second film in the first opening portion is etched by a second etching process. The second film is etched at a higher rate than the first film by the second etching process.

Abstract: In a photolithography system, an illumination assembly to provide intensified uniform illumination includes an illumination source reflector and a plate having an aperture opening therethrough and a mirrored surface thereon, the mirrored surface of the plate confronting the illumination source reflector. The illumination assembly further includes an illumination source for generating illumination disposed between the illumination source reflector and the plate.