Patents by Inventor Junichiro Nikaido

Junichiro Nikaido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9041169
    Abstract: A semiconductor packaging container allowing to use in millimeter band is provided at a low cost. The inner SIG pads and the inner GND pads, capable of a direct connection with a signal terminal of a semiconductor chip 10 are provided on the bottomed cylindrical dielectric case formed of the liquid crystal polymer. Further, the external SIG pads integrally formed with the inner SIG pads 201, 202 and the external GND pad 303 integrally formed with the inner GND pad are provided on the back of the bottom surface of the dielectric case as the external terminal. The inner GND pads and are to form the coplanar waveguide with the inner SIG pads and. Also, the inner GND pads and are to add capacitive reactance for canceling the inductance caused by the space at the semiconductor chip portion to the coplanar waveguide.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 26, 2015
    Assignee: YOKOWO CO., LTD.
    Inventors: Shoichi Koshikawa, Junichiro Nikaido, Shintaro Takase, Yoshio Aoki
  • Publication number: 20140353811
    Abstract: A semiconductor packaging container allowing to use in millimeter band is provided at a low cost. The inner SIG pads and the inner GND pads, capable of a direct connection with a signal terminal of a semiconductor chip 10 are provided on the bottomed cylindrical dielectric case formed of the liquid crystal polymer. Further, the external SIG pads integrally formed with the inner SIG pads 201, 202 and the external GND pad 303 integrally formed with the inner GND pad are provided on the back of the bottom surface of the dielectric case as the external terminal. The inner GND pads and are to form the coplanar waveguide with the inner SIG pads and. Also, the inner GND pads and are to add capacitive reactance for canceling the inductance caused by the space at the semiconductor chip portion to the coplanar waveguide.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 4, 2014
    Applicant: YOKOWO CO., LTD.
    Inventors: Shoichi Koshikawa, Junichiro Nikaido, Shintaro Takase, Yoshio Aoki
  • Patent number: 6800878
    Abstract: At least a channel layer and an etching stopper layer are provided on a semiconductor substrate in order, a gate electrode that Schottky-contacts the etching stopper layer is provided on the etching stopper layer, and InGaP having an In composition ratio of 0.66 through 0.9 is used as the etching stopper layer in a field effect type compound semiconductor device.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: October 5, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Kazuo Nambu, Junichiro Nikaido
  • Publication number: 20030173584
    Abstract: A semiconductor integrated circuit device includes a semiconductor layer on a substrate, a first gate electrode formed on the semiconductor layer, and a second gate electrode that is formed on the semiconductor layer and is adjacent to a sidewall of the first gate electrode along a channel length. The first and second gate electrodes have different work functions.
    Type: Application
    Filed: January 22, 2003
    Publication date: September 18, 2003
    Applicant: FUJITSU QUANTUM DEVICES LIMITED
    Inventor: Junichiro Nikaido
  • Publication number: 20030098477
    Abstract: At least a channel layer and an etching stopper layer are provided on a semiconductor substrate in order, a gate electrode that Schottky-contacts the etching stopper layer is provided on the etching stopper layer, and InGaP having an In composition ratio of 0.66 through 0.9 is used as the etching stopper layer in a field effect type compound semiconductor device.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 29, 2003
    Applicant: FUJITSU QUANTUM DEVICES LIMITED
    Inventors: Kazuo Nambu, Junichiro Nikaido
  • Patent number: 6395588
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜1016 to 1˜1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 28, 2002
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Publication number: 20020008248
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
    Type: Application
    Filed: June 15, 2001
    Publication date: January 24, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Patent number: 6274893
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: August 14, 2001
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno