Abstract: An object of the present invention is to provide a method for directly performing arylation (particularly ?-arylation) of carbonyl or thiocarbonyl compounds using a more inexpensive phenol derivative and nickel catalyst. Another object of the present invention is to provide a novel nickel catalyst that can be used in this method, and a novel ligand of the nickel catalyst. The novel compounds of the present invention are a compound having a diphosphine skeleton in which a five- or six-membered heterocyclic ring is substituted with two dialkylphosphines and/or dicycloalkylphosphines, or a salt thereof, and a compound having the diphosphine skeleton that is bound to nickel. Moreover, coupling reaction of a carbonyl compound and a phenol derivative can be advanced in the presence of a nickel compound having a monodentate or bidentate dialkylphosphine and/or dicycloalkylphosphine skeleton.

Abstract: The present invention is a method for producing a phenyl-substituted heterocyclic derivative represented by general formula (1), which has a step wherein a heteroaromatic compound represented by general formula (2) is reacted with a phenol derivative represented by general formula (3) in the presence of a nickel compound, 1,2-bis(dicyclohexylphosphino)ethane, and a base.

Abstract: The present invention is a method for producing a phenyl-substituted heterocyclic derivative represented by general formula (1), which has a step wherein a heteroaromatic compound represented by general formula (2) is reacted with a phenol derivative represented by general formula (3) in the presence of a nickel compound, 1,2-bis(dicyclohexylphosphino)ethane, and a base.

Abstract: A circuit and a method for generating an address, which can generate a plurality of types of address on the basis of a reference address, and an apparatus for generating an address, which can generate the different addresses from one another by using a plurality of circuits described above at a plurality of steps. The circuit (200) for generating an address, comprises: a multiplex counter (30) comprising a counter (31) for counting a pulse number of a clock signal to generate a count number represented by binary bit and a bit shift circuit (33) for shifting the count number, to generate an output count number; and an arithmetic circuit (20) for operating an address signal on the basis of the output count number and a reference address signal, to output the address signal to a semiconductor memory as an object of test.

Abstract: A circuit and a method for generating an address, which can generate a plurality of types of address on the basis of a reference address, and an apparatus for generating an address, which can generate the different addresses from one another by using a plurality of circuits described above at a plurality of steps. The circuit (200) for generating an address, comprises: a multiplex counter (30) comprising a counter (31) for counting a pulse number of a clock signal to generate a count number represented by binary bit and a bit shift circuit (33) for shifting the count number, to generate an output count number; and an arithmetic circuit (20) for operating an address signal on the basis of the output count number and a reference address signal, to output the address signal to a semiconductor memory as an object of test.

Abstract: A sampling circuit system enhances sampling resolution without increasing frequencies of clock signals for sampling. An input waveform is input to a first group of sampling circuits and a sampling circuit serving as a standard circuit. Clock signals out of phase from each other by 2 .pi./n (n=an integer not less than 3) radian, respectively, against a clock signal input to the standard circuit are input to the first group of sampling circuits for sampling. Then sampling signals output from the first group of the sampling circuits are input to a second group of sampling circuits so as to be sampled again by inputting a sampling signal output from the standard circuit as a common clock signal for the second group of sampling circuits.

Abstract: A phase detector enables sampling of an input waveform such that a resolution, equivalent to the resolution conventionally obtained by doubling a clock frequency, is obtained without doubling the frequency. In order to accomplish this, the phase detector has the following construction and function. A first sampling circuit samples an input waveform using an in-phase clock signal from a clock to generate a sampled waveform. A second sampling circuit samples the input waveform by using a falling edge of the clock to generate an output a signal. A third sampling circuit samples the output signal from the second sampling circuit by a rising edge of the sampled waveform supplied from the first sampling circuit to generate a phase detection flag. This phase detection flag thus detects the presence of the input waveform at a rate double the frequency of the clock.