Abstract: An image pickup apparatus comprises an image pickup unit for photographing an object and generating image data, and a frame forming an outline of the image pickup apparatus, wherein spaces are formed between the image pickup unit and the frame to allow an operator grasp inner planes of the frame.

Abstract: An image pickup apparatus comprises: an image pickup unit for picking up an object image; an image display unit for displaying an image; a grip portion to be grasped by an operator; a moving portion for allowing the grip portion to move between a first position in which the grip portion overlaps part of the image display unit and a second position in which the grip portion does not overlap the image display unit.

Abstract: An image pickup apparatus comprises an image pickup unit for photographing an object and generating image data, and a frame forming an outline of the image pickup apparatus, wherein spaces are formed between the image pickup unit and the frame to allow an operator grasp inner planes of the frame.

Abstract: An image pickup apparatus comprises: an image pickup unit for picking up an object image; an image display unit for displaying an image; a grip portion to be grasped by an operator; a moving portion for allowing the grip portion to move between a first position in which the grip portion overlaps part of the image display unit and a second position in which the grip portion does not overlap the image display unit.

Abstract: A computer which can efficiently perform DMA transfer even if the bus on an input/output adapter side is operating at a high speed and the bus on a main memory side is operating at a low speed. In this computer, the DMA controller functions to prefetch the data to the cache from the main memory and is provided with a prefetch address table holding the prefetch address; an address comparing unit which compares the prefetch address and the input address; a hit recheck control unit which judges if there is a hit in the cache again; and a memory fetch decision unit which instructs the hit recheck control unit to perform a hit recheck when the input address is a cache miss (mis-hit) and a comparison of the input address and the prefetch address shows they coincide while makes a read request to the main memory system when it shows they do not coincide.