Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

Abstract: An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

Abstract: A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.

Abstract: On a transmission path connecting a first semiconductor integrated circuit that is started by a system management apparatus and a second semiconductor integrated circuit that is not started by the system management apparatus, when connection of the first semiconductor integrated circuit to the second semiconductor integrated circuit is detected, after being turned to a first signal state for detecting a valid lane, each lane on the transmission path is turned to a second signal state corresponding to each bit of initial setting code. In the second semiconductor integrated circuit, the first and second signal states are detected for each lane of the transmission path. Based on the detected signal state, after detecting the first signal state, the second signal state is detected and each bit value of the initial setting code is decoded. Based on the decoded initial setting code, an initialization process is executed.

Abstract: A relay device includes a first determining unit, a first sending unit, a receiving unit, a setting unit, a second determining unit, and a second sending unit. When the first determining unit determines that the relay device is a parent node, the first sending unit sends a set value stored in a storing unit to all the other relay devices to which the relay device is connected. When the first determining unit determines that the relay device is not the parent node, the receiving unit receives the set value. The setting unit sets the set value received by the receiving unit in the storing unit. When the second determining unit determines that the received set value has not been sent to the other relay devices, the second sending unit sends the received set value to the other relay devices to which the relay device is connected.

Abstract: When a relaying apparatus receives communication unit data transmitted from a processing apparatus that performs data processing, the relaying apparatus extracts preset data from the received communication unit data as trace information and calculates the number of pieces of the received communication unit data. History information of the received communication unit data is selected from the extracted trace information and statistical information obtained from the result of the calculation. The selected information is recorded in a storage apparatus available to the processing apparatus.

Abstract: A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value.

Abstract: A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.

Abstract: A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data.

Abstract: A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.

Abstract: A signal inversion unit inverts an adjustment pattern signal input as received data. A clock adjustment control circuit acquires a first TAP value adjusted and obtained when a phase adjusting operation is performed on a clock adjustment circuit in a state in which the adjustment pattern signal is not inverted, a first detection frequency of the adjustment pattern signal in a runtime of the operation, a second TAP value adjusted and obtained when the phase adjusting operation is performed in a state in which the adjustment pattern signal is inverted by the signal inversion unit, and a second detection frequency of the adjustment pattern signal in the runtime of the operation. A controller tests an operating state of the phase adjusting operation based on the first and second TAP values and the first and second detection frequencies of the adjustment pattern obtained by the clock adjustment control circuit.

Abstract: A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.

Abstract: A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.

Abstract: A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value.

Abstract: When a new data relaying device that has yet to have configuration information set therein is incorporated, the configuration information of an existing data relaying device is copied to the new data relaying device.

Abstract: A plurality of units (processing units) connected to a crossbar are divided into a plurality of groups and one is selected from requests selected for each group according to priority among the groups that changes at prescribed time intervals. Thus, the number of times per unit time requests issued from units belonging to a group whose priority is improved at the prescribed time intervals can be maintained over a certain value regardless of a request state.

Abstract: A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.

Abstract: A configuration is such as to change a mode setup of other crossbars influenced by an error occurring in one of plural crossbars from a first mode to a second mode for operating each of them independently (i.e., in a singularization mode) in the case of placing plural crossbars (i.e., crossbar units) for connecting incorporated units (i.e., processing units) and operating the plural crossbars in the first mode (i.e., a dualized mode) for dualizing them, thereby continuing an operation of a system by using a normally operable part when an error occurs in a part of the system.

Abstract: According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.

Abstract: A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data.