Patents by Inventor Junji Iwahori
Junji Iwahori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145390Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Hideyuki KOMURO, Junji IWAHORI
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Publication number: 20240113124Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Inventors: Toshio HINO, Junji IWAHORI
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Patent number: 11916056Abstract: A semiconductor integrated circuit device includes a standard cell having a plurality of height regions. A plurality of partial circuits having an identical function and each operating in response to common signals S and NS are arranged in any one of the height regions. A metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits, and a metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits.Type: GrantFiled: October 13, 2020Date of Patent: February 27, 2024Assignee: SOCIONEXT INC.Inventor: Junji Iwahori
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Patent number: 11908799Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.Type: GrantFiled: May 17, 2021Date of Patent: February 20, 2024Assignee: SOCIONEXT INC.Inventors: Hideyuki Komuro, Junji Iwahori
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Patent number: 11881484Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.Type: GrantFiled: January 5, 2023Date of Patent: January 23, 2024Assignee: SOCIONEXT INC.Inventors: Toshio Hino, Junji Iwahori
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Publication number: 20230411396Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.Type: ApplicationFiled: September 5, 2023Publication date: December 21, 2023Inventors: Toshio HINO, Junji IWAHORI
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Patent number: 11799471Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.Type: GrantFiled: December 20, 2022Date of Patent: October 24, 2023Assignee: SOCIONEXT INC.Inventors: Atsushi Okamoto, Hirotaka Takeno, Junji Iwahori
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Patent number: 11784188Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.Type: GrantFiled: June 13, 2022Date of Patent: October 10, 2023Assignee: SOCIONEXT INC.Inventors: Toshio Hino, Junji Iwahori
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Publication number: 20230120959Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Atsushi OKAMOTO, Hirotaka TAKENO, Junji IWAHORI
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Patent number: 11574930Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.Type: GrantFiled: April 20, 2021Date of Patent: February 7, 2023Assignee: SOCIONEXT INC.Inventors: Toshio Hino, Junji Iwahori
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Patent number: 11563432Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.Type: GrantFiled: January 18, 2022Date of Patent: January 24, 2023Assignee: SOCIONEXT INC.Inventors: Atsushi Okamoto, Hirotaka Takeno, Junji Iwahori
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Publication number: 20220392999Abstract: A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.Type: ApplicationFiled: August 16, 2022Publication date: December 8, 2022Inventor: Junji IWAHORI
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Publication number: 20220310658Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Toshio HINO, Junji IWAHORI
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Publication number: 20220246722Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Applicants: SOCIONEXT INC., SOCIONEXT INC.Inventor: Junji IWAHORI
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Patent number: 11398466Abstract: A layout structure of a capacitance cell using vertical nanowire (VNW) FETs is provided. The capacitance cell includes a plurality of first-conductivity type VNW FETs lining up in the X direction, provided between a first power supply interconnect and a second power supply interconnect. The plurality of first-conductivity type VNW FETs include at least one first VNW FET having a top and a bottom connected with the first power supply interconnect and a gate connected with the second power supply interconnect.Type: GrantFiled: July 1, 2020Date of Patent: July 26, 2022Assignee: SOCIONEXT INC.Inventor: Junji Iwahori
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Publication number: 20220231681Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.Type: ApplicationFiled: January 18, 2022Publication date: July 21, 2022Inventors: Atsushi OKAMOTO, Hirotaka TAKENO, Junji IWAHORI
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Publication number: 20220223588Abstract: A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Inventor: Junji IWAHORI
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Patent number: 11387256Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.Type: GrantFiled: October 8, 2020Date of Patent: July 12, 2022Assignee: SOCIONEXT INC.Inventors: Toshio Hino, Junji Iwahori
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Publication number: 20220216319Abstract: In a p-type region, a nanosheet farthest from an n-type region has a face exposed from a first gate interconnect on the side away from the n-type region in the Y direction. In the n-type region, a nanosheet farthest from the p-type region has a face exposed from a second gate interconnect on the side away from the p-type region in the Y direction. In the p-type region, a nanosheet closest to the n-type region has a face exposed from the first gate interconnect on the side closer to the n-type region in the Y direction. In the n-type region, a nanosheet closest to the p-type region has a face exposed from the second gate interconnect on the side closer to the p-type region in the Y direction.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Inventor: Junji IWAHORI
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Matching nanowire FET periodic structuire to standard cell periodic structure in integrated circuits
Patent number: 11348925Abstract: A semiconductor integrated circuit device using nanowire FETs has a circuit block in which a plurality of cell rows each including a plurality of standard cells lined up in the X direction are placed side by side in the Y direction. The plurality of standard cells each include a plurality of nanowires that extend in the X direction and are placed at a predetermined pitch in the Y direction. The plurality of standard cells have a cell height, that is a size in the Y direction, M times (M is an odd number) as large as half the pitch of the nanowires.Type: GrantFiled: December 11, 2019Date of Patent: May 31, 2022Assignee: SOCIONEXT INC.Inventor: Junji Iwahori