Patents by Inventor Junji Kataoka
Junji Kataoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11769810Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.Type: GrantFiled: March 11, 2021Date of Patent: September 26, 2023Assignee: Kioxia CorporationInventors: Junji Kataoka, Tomomasa Ueda, Shushu Zheng, Nobuyoshi Saito, Keiji Ikeda
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Patent number: 11569241Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer. The oxide semiconductor layer includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region in which at least one anion element selected from the group consisting of fluorine and chlorine is contained within a range of 1 atomic % or more and less than 8 atomic % in the metal oxide.Type: GrantFiled: March 5, 2021Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Hiroki Kawai, Junji Kataoka, Keiji Ikeda
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Publication number: 20220223430Abstract: A plasma etching method in an embodiment includes etching a silicon-containing film by using plasma of a hydrofluorocarbon gas. The hydrofluorocarbon gas contains, as a conjugated cyclic compound, hydrofluorocarbon having a composition represented by CxHyFz, where x, y, and z are positive integers satisfying x?6 and (z?y)/x?1).Type: ApplicationFiled: August 25, 2021Publication date: July 14, 2022Applicant: Kioxia CorporationInventors: Junji KATAOKA, Shuichi KUBOI
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Publication number: 20220085182Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.Type: ApplicationFiled: March 11, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Junji KATAOKA, Tomomasa UEDA, Shushu ZHENG, Nobuyoshi SAITO, Keiji IKEDA
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Publication number: 20220068925Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer. The oxide semiconductor layer includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region in which at least one anion element selected from the group consisting of fluorine and chlorine is contained within a range of 1 atomic % or more and less than 8 atomic % in the metal oxide.Type: ApplicationFiled: March 5, 2021Publication date: March 3, 2022Applicant: Kioxia CorporationInventors: Hiroki KAWAI, Junji KATAOKA, Keiji IKEDA
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Patent number: 11024719Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.Type: GrantFiled: September 6, 2019Date of Patent: June 1, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoaki Sawabe, Nobuyoshi Saito, Junji Kataoka, Tomomasa Ueda, Keiji Ikeda
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Patent number: 10950735Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.Type: GrantFiled: March 12, 2019Date of Patent: March 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junji Kataoka, Tomomasa Ueda, Tomoaki Sawabe, Keiji Ikeda, Nobuyoshi Saito
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Publication number: 20200303554Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.Type: ApplicationFiled: September 6, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tomoaki SAWABE, Nobuyoshi SAITO, Junji KATAOKA, Tomomasa UEDA, Keiji IKEDA
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Publication number: 20200013892Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.Type: ApplicationFiled: March 12, 2019Publication date: January 9, 2020Applicant: Toshiba Memory CorporationInventors: Junji KATAOKA, Tomomasa UEDA, Tomoaki SAWABE, Keiji IKEDA, Nobuyoshi SAITO
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Publication number: 20180076311Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.Type: ApplicationFiled: February 24, 2017Publication date: March 15, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu SAITO, Kohei OASA, Takuo KIKUCHI, Junji KATAOKA, Tatsuya SHIRAISHI, Akira YOSHIOKA, Kazuo SAKI
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Patent number: 9917182Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.Type: GrantFiled: February 24, 2017Date of Patent: March 13, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu Saito, Kohei Oasa, Takuo Kikuchi, Junji Kataoka, Tatsuya Shiraishi, Akira Yoshioka, Kazuo Saki
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Publication number: 20170271493Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer containing aluminum located on the first nitride semiconductor layer, a third nitride semiconductor layer with an aluminum concentration higher than that of the second nitride semiconductor layer located on the second nitride semiconductor layer, a drain electrode and a source electrode provided on one of the second nitride semiconductor layer and on the third nitride semiconductor layer, and a gate electrode located between the drain electrode and the source electrode.Type: ApplicationFiled: August 8, 2016Publication date: September 21, 2017Inventors: Akira YOSHIOKA, Takuo KIKUCHI, Junji KATAOKA, Naoharu SUGIYAMA, Hung HUNG, Yasuhiro ISOBE
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Patent number: 9627400Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction.Type: GrantFiled: February 4, 2015Date of Patent: April 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Koshiishi, Junji Kataoka
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Publication number: 20150270282Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction.Type: ApplicationFiled: February 4, 2015Publication date: September 24, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kenji KOSHIISHI, Junji KATAOKA
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Patent number: 9142774Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element.Type: GrantFiled: December 14, 2012Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hidehiko Yabuhara, Takashi Hirotani, Junji Kataoka, Hisashi Kameoka
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Publication number: 20130153850Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element.Type: ApplicationFiled: December 14, 2012Publication date: June 20, 2013Inventors: Hidehiko Yabuhara, Takashi Hirotani, Junji Kataoka, Hisashi Kameoka
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Publication number: 20120070966Abstract: A method for manufacturing a semiconductor element includes etching a surface of a substrate by a dry etching processing, performing a first heat treatment for the surface of the substrate in an atmosphere including halogen, and forming a nitride semiconductor on the surface of the substrate.Type: ApplicationFiled: September 7, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Katsumata, Junji Kataoka, Toshiyuki Terada, Yoshiharu Kouji, Hidenori Hanyu, Norikazu Sugawara, Shinji Onduka