Abstract: A trench isolation structure is fabricated on a silicon substrate by initially depositing a masking layer of nitride having an aperture. A spacer of oxide is then formed on the inner sidewall of the aperture to define a mask window. A trench is formed in the substrate by etching it through the mask window. The spacer is removed to form stepped shoulder portions on upper edges of the trench. A liner of thermal oxide is provided in the trench, followed by deposition of a liner of nitride on an area including the trench and the stepped shoulder portions. The trench is filled with silicon oxide, and the layer of nitride is etched away with hot phosphoric acid.

Abstract: A trench isolation structure is fabricated on a silicon substrate by initially depositing a masking layer of nitride having an aperture. A spacer of oxide is then formed on the inner sidewall of the aperture to define a mask window. A trench is formed in the substrate by etching it through the mask window. The spacer is removed to form stepped shoulder portions on upper edges of the trench. A liner of thermal oxide is provided in the trench, followed by deposition of a liner of nitride on an area including the trench and the stepped shoulder portions. The trench is filled with silicon oxide, and the layer of nitride is etched away with hot phosphoric acid.

Abstract: Isolation trenches, formed on a silicon substrate, are lined with a silicon nitride liner and filled with an insulating filler for isolating MOS transistors from each other. For each MOS transistor, an impurity-doped channel region is formed between adjacent trenches, the channel region having a conductivity type equal to conductivity type of the substrate and a concentration higher than a concentration of the substrate. For each channel region, a pair of heavily doped impurity regions are formed in locations close to the adjacent trenches. The heavily doped regions have a concentration higher than the concentration of the channel region.

Abstract: A semiconductor memory device in which each storage cell can maintain its content or data value stored therein even if power is lost, and the content or data value thus maintained can be produced when power is on. Each storage cell has first and second CMOS inverters constituting a flip-flop circuit. The first inverter is composed of a first MOS driver transistor and a first thin-film load transistor. The second inverter is composed of a second MOS driver transistor and a second thin-film load transistor. The first and second load transistors have control gate electrodes and ferroelectric PZT films, respectively. The PZT films are dielectrically polarized by voltages applied to the control gate electrodes, so that the threshold voltage difference is generated between the first and second thin-film transistors. Due to the threshold voltage difference, the preceding content or state of the cell is maintained, and then, it can be reproduced when power is supplied again.

Abstract: An SRAM having a TFT load element has a gate electrode of the load TFTs disposed between bit lines and channel regions of the load TFTs. The structure avoids formation of a parasitic transistor in which each of the bit lines would act as a gate electrode for the channel region of the TFT load element. The SRAM has a high soft error immunity even at a low supply voltage.

Abstract: A grounding wiring layer is provided on the substantially entire region between driver MOS transistors and load MOS thin film transistors of a flip-flop type memory cell. The contact holes for connecting the gate electrodes of the MOS thin film transistors with storage nodes are formed by providing a side wall on the inner wall of each of the contact hole portions formed in the grounding wiring layer and inter-layer insulating films sandwiching it. Thus, the impedance of the grounding wiring layer can be reduced to stabilize the operation of a miniaturized SRAM memory cell using the load MOS thin film transistors. The resistance against for software error caused by .alpha.-ray can also be improved.

Abstract: A grounding wiring layer is provided on the substantially entire region between driver MOS transistors and load MOS thin film transistors of a flip-flop type memory cell. The contact holes for connecting the gate electrodes of the MOS thin film transistors with storage nodes are formed by providing a side wall on the inner wall of each of the contact hole portions formed in the grounding wiring layer and inter-layer insulating films sandwiching it. Thus, the impedance of the grounding wiring layer can be reduced to stabilize the operation of a miniaturized SRAM memory cell using the load MOS thin film transistors. The resistance against soft error caused by .alpha.-ray can also be improved.

Abstract: A dynamic random access memory device comprises memory cells each implemented by a series combination of a switching transistor and a storage capacitor, peripheral circuits fabricated with component field effect transistors, and word lines coupled to the gate electrodes of the switching transistors, and the gate oxide film of each switching transistor is thicker than the gate oxide film of each component field effect transistor, wherein the word lines are coupled through an oxide film thinner than the gate oxide film of the switching transistor to an impurity region so that undersirable electric charges accumulated in the word lines during the fabrication process are discharged to the impurity region before any damages take place in the gate oxide films of the switching transistors.