Abstract: A microneedle array to be used instead of a syringe has, at a tip side of each microneedle, two or four puncture portions disposed facing each other. The puncture portions each have a part of a side surface of each microneedle as outer surfaces, respectively, and one of the puncture portions is shorter than the other(s). A housing section capable of holding a drug is formed by inner surfaces of the puncture portions of each microneedle. The housing section opens toward the tip side and lateral directions orthogonal to an axis core of each microneedle, and has a central bottom surface at a bottom end. The inner surfaces facing each other and forming the housing section of each microneedle each have a downward slope, with a width between the inner surfaces getting narrower as it goes down from tips of the respective puncture portions toward the central bottom surface.

Abstract: A microneedle array with a performance adequate to be used instead of a syringe has at a tip side of each microneedle 10 two puncture portions 14 and 15 disposed facing each other. The puncture portions 14 and 15 each have a part of a side surface of the microneedle 10 as outer surfaces 12 and 13, respectively, and one of the puncture portions 14 and 15 is shorter than the other. Surrounded by inner surfaces 16 and 17 of the puncture portions 14 and 15 facing each other, a housing section 19 capable of holding a drug is formed. The housing section 19 opens toward the tip side and both lateral directions along an axis core of the microneedle 10, and has a central bottom surface 18 at a bottom end.

Abstract: A single-chip microcomputer is disclosed, which comprises a central processing unit including a programmable counter for storing address data for accessing a first memory and performing operations and control, a register for setting address data of a second memory and a coincidence circuit. When the contents of the register and programmable counter coincide, the coincidence circuit provides an instruction to the central processing unit. Thus, the central processing unit accesses an address of the second memory in lieu of an address of the first memory, in which an undesired instruction in stored, according to data in the first memory. Subsequently, the second memory address is accessed in lieu of the first memory address with the undesired instruction therein.