Abstract: A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.

Abstract: A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.

Abstract: A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.

Abstract: A semiconductor integrated circuit includes a flip-flop circuit, a capacitive element, and a switch circuit. The switch circuit includes a first switch circuit which couples the capacitive element to two nodes of the flip-flop circuit at a first timing, and a second switch circuit which short-circuits ends of the capacitive element connected to the two nodes at a second timing different from the first timing.

Abstract: A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity type, which is located between the first well region and the second well region. The memory cell further includes a first tap diffused layer of the first conductivity type for supplying a potential to the first well region, a second tap diffused layer of the first conductivity type for supplying the potential to the second well region, the first and second tap diffused layers being arranged substantially on a diagonal line in the layout of the SRAM cell, and a metal interconnection connected to the first and second tap diffused layers, the metal interconnection passing on the third well region in the SRAM cell.

Abstract: A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer.

Abstract: A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression.

Abstract: The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted.

Abstract: A semiconductor integrated circuit includes a flip-flop circuit, a capacitive element, and a switch circuit. The switch circuit includes a first switch circuit which couples the capacitive element to two nodes of the flip-flop circuit at a first timing, and a second switch circuit which short-circuits ends of the capacitive element connected to the two nodes at a second timing different from the first timing.

Abstract: A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.

Abstract: A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity type, which is located between the first well region and the second well region. The memory cell further includes a first tap diffused layer of the first conductivity type for supplying a potential to the first well region, a second tap diffused layer of the first conductivity type for supplying the potential to the second well region, the first and second tap diffused layers being arranged substantially on a diagonal line in the layout of the SRAM cell, and a metal interconnection connected to the first and second tap diffused layers, the metal interconnection passing on the third well region in the SRAM cell.

Abstract: The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal (/CEm+1) to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal (CEm+1) to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted.

Abstract: A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression.

Abstract: A semiconductor integrated circuit device includes a first and a second field-effect transistors having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer. Different signals are input to each of the gate electrodes, the substrate potential diffusion layer or the well potential diffusion layer are formed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor.

Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Abstract: A circuit for generating memory cell array block selective signals which select memory cell array blocks included in a semiconductor memory device operable in burst mode, wherein the circuit is operated under the control of a burst mode control signal to generate memory cell array block selective signals sequentially and one by one through different and successive time cycles so that, according to the memory cell array block selective signals sequentially generated, the memory cell array blocks are also sequentially selected one by one through the different and successive time cycles for sequentially supplying a word line driver circuit with the memory cell array block selective signals one by one through the different and successive time cycles whereby memory cells included in different memory cell array blocks are sequentially selected one by one through the different and successive time cycles.

Abstract: A semiconductor memory device includes a burst decode signal generation circuit including a bi-directional loop shift register, an input register corresponding to configuration bits outputted from the first first-order decoder, in which the register captures the corresponding configuration bits, so as to subject each of the configuration bits outputted from the first first-order decoder to a circulation shift by synchronizing with the internal address progress clock in a predetermined direction in accordance with an initial address of the first bits of the address signals, and an initial address even/odd judgment section for judging whether the initial address is even or odd, a plurality of input registers, each of which captures decoded signals outputted from the second first-order decoder in an initial value capturing internal clock, a main decoder which decodes outputs from the input registers and the burst decode signal generation circuit for subsequent output of address selective signals, and a memory ce

Abstract: A semiconductor memory device has a built-in error correction system for correcting undesirably inverted data bits, and the built-in error correction system starts a parity bit generating sequence and an error correcting sequence only when increase of error rate is forecasted, thereby increasing the access speed without sacrifice of the reliability.

Abstract: In a semiconductor static RAM which includes at least one static RAM memory cell connected to a pair of complementary bit lines and each connected to a different word line. A bit line load circuit is connected between the pair of complementary bit lines and a voltage supply potential, and a column selection circuit is connected between the pair of complementary bit lines and a pair of complementary common data bus lines coupled to an input/output data control circuit. The bit line load circuit includes a pair of precharge P-channel insulated gate field effect transistors connected between the voltage supply potential and the pair of complementary bit lines. A bit line equalizing P-channel insulated gate field effect transistor is connected between the pair of complementary bit lines. A gate of each of these P-channel transistors is connected to receive the same internal precharge signal.