Abstract: A charge pump includes a capacitor, a first transistor that is electrically connected between a first terminal of the first capacitor and ground, and a second transistor that is electrically connected between a second terminal of the first capacitor and an output node. During a first operation mode of the charge pump, a voltage that is boosted using the capacitor is output through the output node, and during a second operation mode of the charge pump, the first transistor and the second transistor are maintained in an ON state.

Abstract: A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to generate a first voltage based on a clock signal, a second voltage boosting circuit configured to generate a second voltage lower than the first voltage based on the clock signal, a counter, and a determination circuit. The counter counts a first number of clock cycles of the clock signal during a first period in which the first voltage boosting circuit generates the first voltage and applies the first voltage to the first word line while the second voltage boosting circuit generates the second voltage and applies the second voltage to the second word line, and a second number of clock cycles of the clock signal during a second period in which the first voltage boosting circuit generates the first voltage while the first word line is electrically disconnected from the first voltage boosting circuit.

Abstract: A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to generate a first voltage based on a clock signal, a second voltage boosting circuit configured to generate a second voltage lower than the first voltage based on the clock signal, a counter, and a determination circuit. The counter counts a first number of clock cycles of the clock signal during a first period in which the first voltage boosting circuit generates the first voltage and applies the first voltage to the first word line while the second voltage boosting circuit generates the second voltage and applies the second voltage to the second word line, and a second number of clock cycles of the clock signal during a second period in which the first voltage boosting circuit generates the first voltage while the first word line is electrically disconnected from the first voltage boosting circuit.

Abstract: A voltage generating circuit includes a first booster circuit that generates a first boosted voltage from a voltage supplied to an input thereof, a first transistor having a first terminal electrically connected to the input of the first booster circuit, a second booster circuit that generates a second boosted voltage from a voltage supplied to an input thereof, a second transistor having a first terminal electrically connected to the input of the second booster circuit and a second terminal electrically connected to a voltage source, and a control circuit electrically connected between the voltage source and a second terminal of the first transistor, the control circuit configured to cut off the voltage source from the second terminal of the first transistor in accordance with a voltage level of the voltage source.

Abstract: A charge pump includes a capacitor, a first transistor that is electrically connected between a first terminal of the first capacitor and ground, and a second transistor that is electrically connected between a second terminal of the first capacitor and an output node. During a first operation mode of the charge pump, a voltage that is boosted using the capacitor is output through the output node, and during a second operation mode of the charge pump, the first transistor and the second transistor are maintained in an ON state.

Abstract: A semiconductor memory device includes a memory cell array, a voltage generation circuit that generates a voltage applied to the memory cell array, the voltage generation circuit including a plurality of boosting circuits connected in series between an input terminal and an output terminal, and a switching circuit configured to short-circuit one or more of the boosting circuits to the input terminal, and a control circuit that controls a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.

Abstract: A semiconductor memory device includes a memory cell array, a voltage generation circuit that generates a voltage applied to the memory cell array, the voltage generation circuit including a plurality of boosting circuits connected in series between an input terminal and an output terminal, and a switching circuit configured to short-circuit one or more of the boosting circuits to the input terminal, and a control circuit that controls a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad, a voltage reduction circuit, and a first pump circuit. A first power supply is supplied to the first power supply pad. A second power supply, a voltage of which is higher than that of the first power supply is supplied to the second power supply pad. The voltage reduction circuit reduces the second power supply, generates a first voltage lower than that of the second power supply, and supplies the first voltage to the nonvolatile memory. The first pump circuit generates a voltage higher than that of the second power supply on the basis of the first power supply, and supplies the second voltage to the nonvolatile memory.