Abstract: A terminal to be carried into a moving object includes a first information obtaining unit, a time stamp adding unit, a second information obtaining unit, and an integration unit. The first information obtaining unit obtains positional information of the terminal. The time stamp adding unit adds a timestamp to the positional information obtained by the first information obtaining unit. The second information obtaining unit obtains, from the moving object, the positional information of the moving object having a timestamp added in the same time unit as the timestamp added by the object time stamp adding unit. The integration unit integrates positional information having a timestamp for which no positional information has been obtained by the first information obtaining unit, selectively from the positional information obtained by the second information obtaining unit, with the positional information obtained by the second information obtaining unit.

Abstract: A terminal to be carried into a moving object includes a first information obtaining unit, a time stamp adding unit, a second information obtaining unit, and an integration unit. The first information obtaining unit obtains positional information of the terminal. The time stamp adding unit adds a timestamp to the positional information obtained by the first information obtaining unit. The second information obtaining unit obtains, from the moving object, the positional information of the moving object having a timestamp added in the same time unit as the timestamp added by the object time stamp adding unit. The integration unit integrates positional information having a timestamp for which no positional information has been obtained by the first information obtaining unit, selectively from the positional information obtained by the second information obtaining unit, with the positional information obtained by the second information obtaining unit.

Abstract: A data processing control system has a controller wherein the controller (1) sends every received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to the plurality of data processing devices but holds the received instructions in a queue once the number of instructions being executed or waiting to be executed by the plurality of data processing devices has reached the predetermined number, and (3) when the number of instructions being executed or waiting to be executed by the plurality of data processing devices has become zero by completing the execution thereof, starts sending the queued instructions in sequence to the plurality of data processing devices, and continues to send the queued instructions or every newly received instruction to the plurality of data processing devices until the number of instructio

Abstract: A data storage array device includes redundant data storage devices and a controller. The controller includes a set of instructions issued to the data storage devices; a detector for detecting responses to the set of instructions; a timer; and a processor for monitoring the responses. If the responses from all data storage devices finished within a period set by the timer, the processor completes response processing for the set of instructions at the point when the responses finished. If the responses from all data storage devices are not finished at the end of a period set by the timer, the processor completes response processing for the set of instructions using only the responses that are finished at the end of the period of the timer.

Abstract: An on-line reconstruction processing method for data storage array apparatus which possesses plural segments formed of divided storage areas in plural data storage units and plural parity groups grouped of the segments in the plural data storage units by a specified algorithm, and stores redundancy data into at least one segment of the plural parity groups, has

Abstract: A data storage array device including: a plurality of data storage devices having a redundant information; and a controller that controls the data storage devices,

Abstract: A data processing control system has a controller for receiving an instruction directing a data processing operation, and for causing the received instruction to be executed across a plurality of data processing devices, wherein

Abstract: A data transfer apparatus for DMA-transferring stream data between a memory and each of n ports.

Abstract: A parallel computer comprising a plurality of processor elements and a network interconnecting the same, wherein each of the plurality of processor elements includes: a memory unit including a first area and a second area, the first area storing a program and a data portion allocated to the processor element, the second area having a smaller capacity than the first area and storing working data temporarily; a first data transferring unit for performing a first data transfer, whereby data necessary for an operation are transferred to the second area from the first areas of the other processor elements via the network to form a new data portion therein; a processor for performing a first operation, whereby the data portion in the first area is processed as per program and an operation result is restored into the first area, and for performing a second operation, whereby the new data portion in the second area is processed as per program and an operation result is restored into the second area; and a second data

Abstract: A processor element is provided with a data transfer control circuit that sends out an address count pulse (ACNT) onto a control bus. N data transfer channels each contain a data transfer buffer and a buffer control circuit. The buffer control circuit comprises an identification number register, an input/output control circuit, an address counter, and a comparison circuit. The address counter holds a channel address that is preset in such a way as to allow each channel to take the same channel address number, and increments such a channel address each time it receives the ACNT. If the identification number and the channel address coincide, the data transfer buffer in the same channel is selected. The number of interconnecting wires can be reduced and the transfer of data can be carried out at a high transfer rate, in a multiprocessor system whose linking network between each processor is formed by a series of data transfer channels.

Abstract: In a data transfer control device for controlling a data transfer bus connected to plural buffer units, an address generation circuit for specifying a buffer unit address is provided with an address register for holding upper and lower limit values of the buffer unit address, an address counter which sequentially increments the buffer unit address, starting from the lower limit value, and a comparator for judging whether an output of the address counter reaches to the upper limit value. The data transfer control device composes a crossbar-type data transfer network together with the buffer units, and plural processor elements or plural I/O devices are connected to the network.

Abstract: A transfer feeder for hot-forging presses having a clamping mechanism to move two parallel feed bars in the clamp and unclamp directions, an advancing mechanism to move them in the advance and return directions, and a lifting mechanism to raise and lower them. The two feed bars are connected to an inner frame via a pair of parallel links and a pair of supporting links, the inner frame is rockably supported on an intermediate frame in the advance and return directions, the intermediate frame is supported on the outer frame to be freely raised and lowered in relation to the outer frame, the clamping mechanism is so constructed as to rock parallel links in the clamp and unclamp directions, the advancing mechanism is so constructed as to rock the inner frame in relation to the intermediate frame, and the lifting mechanism is so constructed as to raise and lower the intermediate frame in relation to the outer frame.

Abstract: A twist-forming process and a coining process for a crank shaft are carried out by using one twist-forming press including a twist forming section and a coining section, and a stopper height adjusting means for determining the crank pin arrangement and for finely adjusting the twist angles is integrally incorporated into the twist-forming press.