Patents by Inventor Junji Nishioka

Junji Nishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system
    Patent number: 6092173
    Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: July 18, 2000
    Assignees: Fujitsu Limited, PFU Limited
    Inventors: Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Yozo Nakayama, Jun Sakurai, Toshiyuki Muta, Takayuki Shimamura
  • Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system
    Patent number: 6038674
    Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: March 14, 2000
    Assignees: Fujitsu Limited, PFU Limited
    Inventors: Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura
  • Coherence apparatus for cache of multiprocessor
    Patent number: 5890217
    Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: March 30, 1999
    Assignees: Fujitsu Limited, PFU Limited
    Inventors: Akira Kabemoto, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura, Hirohide Sugahara, Junji Nishioka, Takatsugu Sasaki, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Hiroaki Ishihata, Takeshi Horie, Toshiyuki Shimizu