Patents by Inventor Junji Orimoto

Junji Orimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030211640
    Abstract: A system is provided for maintaining plural different process flows for manufacturing different kinds of semiconductor device respectively on a semiconductor production line. The plural different process flows are registered in an automatic process control system. The system includes a function unit for setting an automatic process control in the automatic process control system based on an automatic process control information for each of the plural different process. The automatic control information for each of the plural different process flows further includes a process flow name, and process names respectively unique to the single process flow.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 13, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Junji Orimoto
  • Patent number: 6584371
    Abstract: A lot-base management host computer performs management of wafers with a lot as a unit by managing a process condition for each lot, a correspondence between a carrier ID and a lot ID, and a correspondence between a slot ID and a wafer ID in each lot. A wafer-base management host computer performs management for each wafer in a lot by managing a process condition corresponding to a wafer number in a lot. Further, a converted condition instructing section transmits data acquired from the lot-base management host computer and the wafer-base management host computer to a semiconductor fabrication apparatus. The wafer-base management host computer stores a process condition for each level and a machine number of a semiconductor fabrication apparatus in use in the form of a matrix as an experimental level master and issues a process condition as instructions to the semiconductor fabrication apparatus through the converted condition instructing section according to the experimental level master.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: June 24, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Toshihiro Sada, Junji Orimoto