Abstract: There is provided a trace/failure observation system which is capable of comprehensive collection of information that is needed for checking a desired operation in a system or the like where the amount of information to be observed is large, and which allows easy analysis of the desired operation. The system includes, in a system LSI to be subjected to trace/failure observation: an event detecting means for observing behavior of a portion to be observed; a first data reducing means for performing observation data reduction processing so that observation data from the event detecting means has an amount of information processable to a second data reducing means; and the second data reducing means for performing one or more steps of observation data reduction processing.

Abstract: Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory. The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20aA through 20n from each other.

Abstract: Provided is the access control system for controlling an access on a task basis without modifying a device side to be accessed and without applying a task ID at each access to a device. The access filter system for controlling an access between devices mounted on an electronic device, which comprises the access control unit for applying a unique device key set for each device as a right to access the device on a basis of a task operable on the electronic device and determining whether to allow an access to the device according to whether an access request task which requests an access to the device has the device key.

Abstract: Upon receiving debugging program activation instructions sent from a communication port (1), debugging program activation instruction distribution units (61 and 71) distribute the received debugging program activation instructions to execution units designated by these activation instructions. Debugging program activation units (62 and 72) are provided for each execution unit (A and B) and, based on the activation instructions distributed by the activation instruction distribution units (61 and 71), activate debugging programs (63 and 73) on the execution units designated by these activation instructions.

Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.

Abstract: In a parallel processing system by an OS for single processors which operates an OS for single processors and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, with the multiprocessor being logically divided into two groups of a first processor side and a second processor side, a unit of work that can be parallelized within the application operating on a processor on the first processor side is controlled as a new unit of work on a processor on the second processor side.

Abstract: On a parallel processing system which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, an OS service unit which provides services of the OS for single processors to a unit of work which can be parallelized within the application controls security function with respect to a processing request from the unit of work in response to the processing request.

Abstract: In the application parallel processing system, on specific one of processors forming a multi-processor, an application is operated independently of other processors and on other processors, a function expansion module is operated in parallel processing under control of the application. As a result, even in such a data processing device internally provided with a processor whose processing capacity is small as a portable terminal, applications can be operated smoothly.

Abstract: The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.

Abstract: The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.

Abstract: In a parallel processing system by an OS for single processors which operates an OS for single processors and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, with the multiprocessor being logically divided into two groups of a first processor side and a second processor side, a unit of work that can be parallelized within the application operating on a processor on the first processor side is controlled as a new unit of work on a processor on the second processor side.

Abstract: In a parallel processing system by an OS for single processors which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, a processor on a first processor side receives a request for activating or stopping a processor from a unit of work on any of the processors and controls a power supply management device of the OS for single processors to conduct activation or stop of the requested processor, while the processor requested to be activated or stop executes processing necessary for the activation or stop based on a notification from the first processor side.

Abstract: A device and a method are provided for increasing processing speed and for ensuring system security when an application or a driver is added. The device includes a first CPU group 10A that executes software 20A composed of basic processing 22 and an OS 21A; a second CPU group 10B that executes software 20B composed of additional processing 23 and OS 21B corresponding to the additional processing, inter-processor communication means 40, and 402 used for communication between the first CPU 10A and the second CPU 10B, and access control means 30 that controls access made by the second CPU 10B to a memory 50 and/or an input/output device 60.

Abstract: A telephone directory information modifying apparatus which makes use of backup data, which is a backup of telephone directory information of portable telephones and held at a data center, to permit mutual operation accompanying telephone number change.

Abstract: The invention provides a program conversion apparatus which performs parallelization for a multi-thread microprocessor on an intermediate program level. A parallelization apparatus of the program conversion apparatus includes a fork spot determination section, a register allocation section and an instruction reordering section. The fork spot determination section determines a fork spot and a fork system based on a result of a register allocation trial performed by the register allocation section, the number of spots at which memory data dependence is present, and branching probabilities and a data dependence occurrence frequency obtained from a profile information file. The instruction reordering section reorders instructions preceding to and succeeding the FORK instruction in accordance with the determination.

Abstract: On a parallel processing system by an OS for single processors which operates, on a multiprocessor, an OS for single processors and an existing application to realize parallel processing by the multiprocessor with respect to the application, each processor includes a communication proxy unit which transfers data between tasks spreading over the processors by proxy and the communication proxy unit on a processor in which a task on a transmission side operates holds information about an address, on a processor, of a task on a reception side to receive data transferred from the task on the transmission side as proxy for the task on the reception side.

Abstract: On a parallel processing system which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, an OS service unit which provides services of the OS for single processors to a unit of work which can be parallelized within the application controls security function with respect to a processing request from the unit of work in response to the processing request.

Abstract: In a parallel processing system by an OS for single processors which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, a processor on a first processor side receives a request for activating or stopping a processor from a unit of work on any of the processors and controls a power supply management device of the OS for single processors to conduct activation or stop of the requested processor, while the processor requested to be activated or stop executes processing necessary for the activation or stop based on a notification from the first processor side.

Abstract: The invention provides a program conversion apparatus which performs parallelization for a multi-thread microprocessor on an intermediate program level. A parallelization apparatus of the program conversion apparatus includes a fork spot determination section, a register allocation section and an instruction reordering section. The fork spot determination section determines a fork spot and a fork system based on a result of a register allocation trial performed by the register allocation section, the number of spots at which memory data dependence is present, and branching probabilities and a data dependence occurrence frequency obtained from a profile information file.