Patents by Inventor Junji Seino

Junji Seino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile semiconductor memory device
    Patent number: 6147905
    Abstract: A non-volatile semiconductor memory device includes memory cell blocks in which n sectors for erasing are defined where n is an integer equal to or greater than 1. Each of the memory cell blocks includes sense amplifiers, and an activation signal generating circuit activating an activation signal for generating the sense amplifiers. Data held in the sense amplifiers of the memory cell blocks are continuously output in accordance with a burst length. Sectors related to blocks corresponding to the burst length are sequentially subjected to an erase operation.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Junji Seino
  • MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin
    Patent number: 5734622
    Abstract: An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. A MOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: March 31, 1998
    Assignee: Fujitsu Limited
    Inventors: Kazuto Furumochi, Junji Seino
  • MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin
    Patent number: 5644546
    Abstract: An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. AMOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.
    Type: Grant
    Filed: August 10, 1995
    Date of Patent: July 1, 1997
    Assignee: Fujitsu Limited
    Inventors: Kazuto Furumochi, Junji Seino