Patents by Inventor Junji Shiota

Junji Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9607861
    Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 28, 2017
    Assignee: AOI ELECTRONICS CO., LTD.
    Inventors: Junji Shiota, Ichiro Kono
  • Publication number: 20160233111
    Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).
    Type: Application
    Filed: February 4, 2016
    Publication date: August 11, 2016
    Applicant: TERA PROBE, INC.
    Inventors: Junji SHIOTA, Ichiro KONO
  • Patent number: 8564128
    Abstract: A semiconductor device comprises a semiconductor substrate having a connection pad, an external connection electrode provided on the semiconductor substrate to be connected to the connection pad, and a sealing film provided to cover the external connection electrode, wherein an opening is provided in the sealing film to expose a center of the upper surface of the external connection electrode, and the sealing film is provided to cover an outer peripheral part of the upper surface of the external connection electrode.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: October 22, 2013
    Assignee: Teramikros, Inc.
    Inventor: Junji Shiota
  • Patent number: 8354349
    Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: January 15, 2013
    Assignee: Casio Computer Co., Ltd.
    Inventor: Junji Shiota
  • Patent number: 8154133
    Abstract: A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 10, 2012
    Assignee: Casio Computer Co., Ltd.
    Inventors: Taisuke Koroku, Takeshi Wakabayashi, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Publication number: 20120074564
    Abstract: A semiconductor device comprises a semiconductor substrate having a connection pad, an external connection electrode provided on the semiconductor substrate to be connected to the connection pad, and a sealing film provided to cover the external connection electrode, wherein an opening is provided in the sealing film to expose a center of the upper surface of the external connection electrode, and the sealing film is provided to cover an outer peripheral part of the upper surface of the external connection electrode.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 29, 2012
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Junji SHIOTA
  • Patent number: 7863750
    Abstract: In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 4, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Junji Shiota, Taisuke Koroku, Nobumitsu Fujii, Osamu Kuwabara, Osamu Okada
  • Publication number: 20100173455
    Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 8, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventor: Junji Shiota
  • Publication number: 20100144096
    Abstract: First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicants: Casio Computer Co., Ltd.
    Inventors: Taisuke Koroku, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Publication number: 20100144095
    Abstract: First, a trench formed in parts of a semiconductor wafer, a sealing film and others corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entirety including the separated silicon substrates from being easily warped.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventors: Taisuke KOROKU, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Publication number: 20100144097
    Abstract: First, a trench is formed in parts of a semiconductor wafer, a sealing film and other elements corresponding to a dicing street and both sides thereof. In this state, the semiconductor wafer is separated into silicon substrates by the formation of the trench. Then, a resin protective film is formed on the bottom surface of each silicon substrate including the inner part of the trench. In this case, the semiconductor wafer is separated into the silicon substrates. However, a support plate is affixed to the upper surfaces of the columnar electrode and the sealing film via an adhesive layer. Therefore, when the resin protective film is formed, it is possible to prevent the entire workpiece including the separated silicon substrates from being easily warped.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicants: CASIO COMPUTER CO., LTD.
    Inventors: TAISUKE KOROKU, OSAMU OKADA, OSAMU KUWABARA, JUNJI SHIOTA, NOBUMITSU FUJII
  • Publication number: 20100019371
    Abstract: In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 28, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventors: Junji SHIOTA, Talsuke Koroku, Nobumitsu Fujii, Osamu Kuwabara, Osamu Okada
  • Publication number: 20090243097
    Abstract: A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Taisuke KOROKU, Takeshi Wakabayashi, Osamu Okada, Osamu Kuwabara, Junji Shiota, Nobumitsu Fujii
  • Publication number: 20080073785
    Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, Columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 27, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventor: Junji Shiota
  • Patent number: 6473966
    Abstract: A printer head substrate having a silicon substrate on which heat generating elements and partitions are formed and an orifice plate which adhered to the partitions is placed on a stage of a helicon-wave dry etching system. Helicon-wave dry etching is performed while cooling the printer head substrate by allowing a coolant gas to be intervened between the substrate and the stage. This allows multiple orifices of a desired and adequate shape to be simultaneously and quickly bored in the orifice plate even if a thin film sheet having adhesive layers adhered to both sides thereof is used as the orifice plate, thereby improving the working efficiency.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 5, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ichiro Kohno, Junji Shiota, Hideki Kamada, Satoshi Kanemitsu, Yoshihiro Kawamura
  • Patent number: 6368515
    Abstract: In a method of manufacturing an ink-jet printer which uses a thin film sheet having adhesive layers respectively formed on the top and bottom sides, as an orifice plate, orifices are formed in the ink-ejecting side of the thin film sheet after the adhesive layer on that ink-ejecting side has been removed. This prevents the formation of the orifices from being adversely affected by any otherwise residual of the adhesive layer and can thus permit accurate formation of orifices of a desired shape. Even if helicon-wave dry etching which ensure fast etching using high-power energy is used to form orifices, therefore, no adhesive layer is thermally expanded to be a residual so that multiple orifices can be formed simultaneously and quickly.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 9, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Katsuzo Kaminishi, Junji Shiota, Ichiro Kohno, Kazuyoshi Arai
  • Patent number: 6320138
    Abstract: A wiring substrate is disclosed, which has optimal characteristics for, for example, an active matrix type liquid crystal display device with a thin film transistor. Wiring formed of an Al-Nd-Ti alloy thin film is formed on a glass substrate, and if necessary, a semiconductor element which is electrically connected to the wiring is formed. In this case, the specific resistance of the Al-Nd-Ti alloy thin film is about 8 &mgr;&OHgr; cm if the Nd concentration is 0.75 at % and the Ti concentration is 0.5 at %. Further, even if the resultant substrate is heated at 240-270 C. after the formation of the wiring, occurrence of a hillock and a pinhole is substantially completely suppressed.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: November 20, 2001
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kenji Kamiya, Junji Shiota
  • Patent number: 5514259
    Abstract: A sputtering apparatus has a pressure resistant vessel, from which gas in discharged and into which gas for sputtering is supplied, a substrate disposed in the vessel to be formed with a film at one surface thereof, a target disposed oppositely to one surface of the substrate to be formed of a substance to become a material of the film, a magnet provided on the surface of the target oppositely to the substrate to generate a magnetic field for confining a plasma in the vicinity of the surface of the target opposed to the substrate, a plate-shaped anode disposed between the substrate and the target to be formed with an opening of the shape in which at least one side is larger than the profile of the substrate at a position opposed to the substrate, and a sputtering current supplier between the anode and the target. The anode is made of a conductor. An opening larger than the profile of the substrate is formed at a position of the anode opposed to the substrate.
    Type: Grant
    Filed: November 26, 1993
    Date of Patent: May 7, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventors: Junji Shiota, Ichiro Ohno, Hidetaka Uchiumi
  • Patent number: 5441352
    Abstract: A tape cutting device includes a fixed blade fixed to a frame and a movable blade fixed to a manually pivotable lever. A printing operation to the print tape is performed by a print head and a platen. In this case, the tape runs by the rotation of the press roller and a tape feed roller, those being driven by a driving motor 2 through a power transmitting portion including a gear train. A gear of the gear train is associated with a tape cutting prevention mechanism including a stop lever. When the tape printing operation is carried out, the stop lever is movable to a first pivot position where the manually pivotable lever is abuttable on the stop lever to prevent the manually pivotable lever to be angularly rotated. When the tape is to be cut, the stop lever is moved to a second pivot position offset from the manually pivotable lever. Thus, the movable blade can be moved toward the fixed blade to cut the tape.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: August 15, 1995
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Junji Shiota
  • Patent number: 5367179
    Abstract: A thin-film transistor comprises a gate electrode formed on an insulating substrate, a gate insulating film covering the gate electrode and the insulating substrate, an i-type semiconductor layer formed on the gate insulating film, and a source electrode and a drain electrode electrically connected to two ends of the i-type semiconductor layer, respectively. The gate electrode is made of aluminum alloy containing high-melting-point metal such as Ti and Ta and oxygen or nitrogen or both.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: November 22, 1994
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hisatoshi Mori, Syunichi Sato, Naohiro Konya, Ichiro Ohno, Hiromitsu Ishii, Kunihiro Matsuda, Junji Shiota